Since early this year, I’ve been working on a BSP project. The biggest challenge was understanding physical memory layout, specifically why certain addresses are defined in the DTS and don’t fall within other expected ranges.
To tackle this, I created a complete memory map of the chip1,which helped me gain a clear understanding, and use the resources of the reference board2to explain.
Fortunately, NXP has made the kernel source and reference manuals for the S32G3 chipset publicly available. This allows us to practice designing memory map diagrams freely using these resources—big thanks to NXP!
The image below shows the complete memory map, including kernel-reserved memory regions.
The S32G3 chip includes five categories of memory ranges:
- Extended Address Map
- External DRAM
- Peripherals
- RAM
- QSPI Memory
Extended Address Map
A 4GB DRAM can be mapped within a 32-bit address space. However, since the lower half of this range is allocated to peripherals, only up to 2GB is available for DRAM.
To overcome this limitation, the system can extend the address space to 40-bit mode. This allows more than 2GB of DRAM to be mapped and provides additional address space for other devices, including the PCIe endpoint as shown in the diagram.
External DRAM
This is the basic range where DRAM is mapped. It serves as the main memory used by the kernel, where tasks like loading the kernel image during boot, memory management like the page allocation.
Peripherals
This range is where most peripherals are mapped to specific areas of the SoC, allowing access to their controllers.
RAM
It’s integrated into SoC chips because key components like PCIe, CPU, and GPU need ultra-high-speed communication. Its size is quite limited compared to DRAM, typically ranging from KB to MB, due to the high cost of larger capacities. This type of memory is commonly used for cache and CPU registers, where ultra-high speed is essential.
QSPI Flash Memory
A QSPI-interfaced flash memory is used to store resources such as pre/boot loaders, kernel images, and additional binaries. This area is used by the M7 cores to store their firmware.
However, the actual accessible address size on the board is limited to0x03FF_FFFF(64MB), even though the total address space extends up to0x1FFF_FFFF(512MB), because the NOR flash3is designed as a 64MB storage.
Conclusion
We have been exploring the memory map of the chip. This can be challenging for BSP newcomers, but it’s essential knowledge. For instance, U-Boot, a bootloader uses environment variables such asloadaddrandfdtaddrto load binaries into DRAM. In such cases, understanding the accessible memory range is crucial.
I hope you found this post helpful and insightful!
