Blackfin

This article is about the DSP microprocessor. For other uses, seeBlackfin (disambiguation).

Blackfinis a family of 16-/32-bitmicroprocessorsdeveloped, manufactured and marketed byAnalog Devices.The processors have built-in, fixed-pointdigital signal processor(DSP) functionality performed by 16-bitmultiply–accumulates(MACs), accompanied on-chip by amicrocontroller.It was designed for a unifiedlow-power processorarchitecture that can runoperating systemswhile simultaneously handling complex numeric tasks such asreal-timeH.264video encoding.

Blackfin

Designer	Analog Devices
Bits	32-bit
Introduced	2000(2000)
Design	RISC
Type	Load–store
Encoding	Variable(16- or 32-bit general purpose, or 64-bit parallel issue of 1 × 32-bit instruction + 2 × 16-bit instructions)
Branching	Condition code
Endianness	Little
Registers
General-purpose	8 × 32-bit data registers (addressable as 16 × 16-bit half-registers), 2 × 40-bit accumulators, 6 × 32-bit address registers, stack pointer, frame pointer

Blackfin

ADI Blackfin Logo
General information
Launched	2008
Discontinued	Present
Marketed by	Analog Devices
Designed by	Analog Devices
Common manufacturer	Analog Devices

Architecture details

Blackfin processors use a32-bitRISCmicrocontrollerprogramming model on aSIMDarchitecture, which was co-developed byIntelandAnalog Devices,as MSA (Micro Signal Architecture).

The architecture was announced in December 2000, and first demonstrated at the Embedded Systems Conference in June, 2001.

It incorporates aspects of ADI's olderSHARCarchitecture and Intel'sXScalearchitecture into a single core, combining digital signal processing (DSP) and microcontroller functionality. There are many differences in the core architecture between Blackfin/MSA and XScale/ARM or SHARC, but the combination was designed to improve performance, programmability and power consumption over traditional DSP or RISC architecture designs.

The Blackfin architecture encompasses various CPU models, each targeting particular applications.The BF-7xx series, introduced in 2014, comprise the Blackfin+ architecture, which expands on the Blackfin architecture with some new processor features and instructions.

Architecture features

Core features

mounted Blackfin BF526 in anAgilentoscilloscope

What is regarded as the Blackfin "core" is contextually dependent. For some applications, theDSPfeatures are central. Blackfin has two 16-bit hardwareMACs,two 40-bitALUsandaccumulators,a 40-bitbarrel shifter,and four 8-bit video ALUs; Blackfin+ processors add a 32-bit MAC and 72-bit accumulator. This allows the processor to execute up to three instructions per clock cycle, depending on the level ofoptimizationperformed by thecompilerorprogrammer.Two nestedzero-overhead loopsand four circular buffer DAGs (data address generators) are designed to assist in writing efficient code requiring fewerinstructions.Other applications use theRISCfeatures, which include memory protection, different operating modes (user, kernel), single-cycleopcodes,data and instruction caches, and instructions for bit test, byte, word, or integer accesses and a variety of on-chip peripherals.

TheISAis designed for a high level ofexpressiveness,allowing the assembly programmer (orcompiler) to optimize an algorithm for the hardware features present. The standard Blackfin assembly language is written using an algebraic syntax: instead of prefix commands used in many other assembly languages.

Other assembly languages	Blackfin assembly language
ldR0,8[P0]	R0 = [P0 + 8]
addR0,R1,R2	R0 = R1 + R2
pushR7	[SP--] = R7

Memory and DMA

The Blackfin uses abyte-addressable,flatmemory map.Internal L1 memory, internal L2 memory, external memory and all memory-mappedcontrol registersreside in this 32-bit address space, so that from a programming point of view, the Blackfin has aVon Neumann architecture.

The L1 internalSRAMmemory, which runs at the core-clock speed of the device, is based on aHarvard architecture.Instruction memory and data memory are independent and connect to the core via dedicated memory buses, designed for higher sustaineddata ratesbetween the core and L1 memory.

Portions of instruction and data L1 SRAM can be optionally configured as cache independently.

Certain Blackfin processors also have between 64KB and 256KB of L2 memory. This memory runs slower than the core clock speed. Code and data can be mixed in L2.

Blackfin processors support a variety of external memories includingSDRAM,DDR-SDRAM,NOR flash,NAND flashandSRAM.Some Blackfin processors also include mass-storage interfaces such asATAPIandSD/SDIO.They can support hundreds of megabytes of memory in the external memory space.

Coupled with the core and memory system is aDMAengine that can operate between any of itsperipheralsand main (or external) memory. The processors typically have a dedicatedDMA channelfor each peripheral, which is designed for higherthroughputfor applications that can use it, such as real-time standard-definition (D1) video encoding and decoding.

Microcontroller features

The architecture of Blackfin contains the usual CPU, memory, and I/O that is found onmicroprocessorsormicrocontrollers.These features enable operating systems.

All Blackfin processors contain aMemory Protection Unit(MPU). The MPU provides protection and caching strategies across the entire memory space. The MPU allows Blackfin to support operating systems,RTOSsand kernels likeThreadX,μC/OS-II, orNOMMU Linux.Although the MPU is referred to as aMemory Management Unit(MMU) in the Blackfin documentation, the Blackfin MPU does not provideaddress translationlike a traditional MMU, so it does not supportvirtual memoryor separate memory addresses per process. This is why Blackfin currently can not support operating systems requiring virtual memory such asWinCEorQNX.

Blackfin supports threerun-time modes:supervisor, user and emulation. In supervisor mode, all processor resources are accessible from the running process. However, when in user mode, system resources and regions of memory can be protected (with the help of the MPU). In a modern operating system or RTOS, the kernel typically runs in supervisor mode and threads/processes will run in user mode. If a thread crashes or attempts to access a protected resource (memory, peripheral, etc.) anexceptionwill be thrown and the kernel will then be able to shut down the offending thread/process. The official guidance from ADI on how to use the Blackfin in non-OS environments is to reserve the lowest-priorityinterruptfor general-purpose code so that all software is run in supervisor space.

Blackfin uses a variable-lengthRISC-like instruction set consisting of 16-, 32- and 64-bit instructions. Commonly used control instructions are encoded as 16-bit opcodes while complex DSP and mathematically intensive functions are encoded as 32- and 64-bit opcodes. This variable length opcode encoding is designed forcode densityequivalence to modern microprocessor architectures.

Media-processing features

The Blackfin instruction set contains media-processing extensions to help accelerate pixel-processing operations commonly used invideo compressionandimage compressionand decompression algorithms.

Peripherals

Blackfin processors contain an array of connectivity peripherals, depending on the specific processor:

• ATAPI
• CAN:A wide-area, low-speed serial bus used in some automotive and industrial electronics
• DMAwith support for memory-to-memory DMA and peripheral DMA
• EMAC (EthernetMedia Access Controller) withMIIandRMII
• External memory: the EBIU (External Bus Interface Unit) can include a controller for SDRAM, Mobile SDRAM, DDR1, DDR2, or LPDDR, and an asynchronous memory controller for SRAM, ROM, flash EPROM, and memory-mapped I/O devices
• GPIOincluding level-triggered and edge-triggered interrupts
• I²C,also known as TWI (Two-Wire Interface): a lower speed, shared serial bus
• MXVR: aMOSTNetwork Interface Controller
• NAND flash
• PPI:A parallel input/output port that can be used to connect to LCDs, video encoders (video DACs), video decoders (video ADCs), CMOS sensors, CCDs and generic, parallel, high-speed devices. The PPI can run up to 75 MHz and can be configured from 8 to 16-bits wide.
• PWMand timers/counters
• Real-time clock
• SD/SDIO
• SPI:a fast serial bus used in some high-speed embedded electronics applications
• SPORT: A synchronous, high speed serial port that can supportTDM,I²Sand a number of other configurable framing modes for connection toADCs,DACs,other processors, FPGAs, etc.
• UART:allows for bi-directional communication withRS-232devices (PCs, modems, PC peripherals, etc.),MIDIdevices,IRDAdevices
• USB 2.0 OTG (On-The-Go)
• Watchdog timer

All of the peripheral control registers arememory-mappedin the normal address space.

Development tools

Blackfin BF537 EZ-Kit-Lite evaluation platform

ADI provides its own software developmenttoolchains.The original VisualDSP++IDEis still supported (its last release was 5.1.2 in October 2014(2014-10)), but is approaching end of life and has not had support added for the new BF6xx and BF7xx processors. The newer toolchain is CrossCore Embedded Studio, which uses supports all Blackfin and Blackfin+ processors using upgraded versions of the same compiler and tools internally, but with a UI based onEclipse CDT.No free version of either tool is available; a single-user license for VisualDSP++ costs $3500 USD, and CrossCore Embedded Studio $995 USD.

Other options includeGreen Hills Software's MULTI IDE and the GNUGCCToolchain for the Blackfin processor family. However, like VisualDSP++, these have not been updated to support the newer BF6xx and BF7xx processors. Moreover, neither support all BF5xx processors. Green Hills MULTI lacks support for BF50x, BF51x, some BF52x, BF547, and BF59x. GCC lacks support for BF50x, BF566, and BF59x, and has incomplete support for BF561.

Blackfin is also supported byNational Instruments'LabVIEWEmbedded Module, which requires VisualDSP++.

Supported operating systems, RTOSs and kernels

Several commercial and open-source operating systems support running on Blackfin.

OS/RTOS/Kernels on Blackfin

Title	License	Comments
ThreadX	Proprietary
Nucleus	Proprietary
μC/OS-II	Proprietary
INTEGRITY	Proprietary
RTEMS	BSD-2 Clause and Permissive
RTXC Quadros	Proprietary
VDK	Proprietary	ADI's real-time kernel. Ships with VisualDSP++.
.NET Micro Framework	Apache License 2.0	Stand-alone version from Microsoft. Integrated version from AxiomFount.

Blackfin was previously supported byμClinuxand later byLinuxwith the NOMMU feature, but as it was not ever widely used and no longer had a maintainer,support was removed from Linux on April 1, 2018; 4.16 was the last release to include Blackfin support.

See also

• SHARC
• TigerSHARC

External links

• Blackfin processor website
• Blackfin Processor Programming Reference
• blackfin.uclinux.orgOpen source tools and Linux kernel for Blackfin
• T2 SDEA build-system supporting the cross compilation to Blackfin