Wikipedia

Non-uniform memory access

Non-uniform memory access(NUMA) is acomputer memorydesign used inmultiprocessing,where the memory access time depends on the memory location relative to the processor. Under NUMA, a processor can access its ownlocal memoryfaster than non-local memory (memory local to another processor or memory shared between processors).[1]NUMA is beneficial for workloads with high memorylocality of referenceand lowlock contention,because a processor may operate on a subset of memory mostly or entirely within its own cache node, reducing traffic on the memory bus.[2]

The motherboard of anHP Z820workstation with two CPU sockets, each with their own set of eightDIMMslots surrounding the socket.

NUMA architectures logically follow in scaling fromsymmetric multiprocessing(SMP) architectures. They were developed commercially during the 1990s byUnisys,Convex Computer(laterHewlett-Packard),HoneywellInformation Systems Italy (HISI) (laterGroupe Bull),Silicon Graphics(laterSilicon Graphics International),Sequent Computer Systems(laterIBM),Data General(laterEMC,nowDell Technologies),Digital(laterCompaq,thenHP,nowHPE) andICL.Techniques developed by these companies later featured in a variety ofUnix-likeoperating systems,and to an extent inWindows NT.

The first commercial implementation of a NUMA-based Unix system was[where?][when?]the Symmetrical Multi Processing XPS-100 family of servers, designed by Dan Gielan of VAST Corporation forHoneywell Information SystemsItaly.

Overview

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One possible architecture of a NUMA system. The processors connect to the bus or crossbar by connections of varying thickness/number. This shows that different CPUs have different access priorities to memory based on their relative location.

Modern CPUs operate considerably faster than the main memory they use. In the early days of computing and data processing, the CPU generally ran slower than its own memory. The performance lines of processors and memory crossed in the 1960s with the advent of the firstsupercomputers.Since then, CPUs increasingly have found themselves "starved for data" and having to stall while waiting for data to arrive from memory (e.g. for Von-Neumann architecture-based computers, seeVon Neumann bottleneck). Many supercomputer designs of the 1980s and 1990s focused on providing high-speed memory access as opposed to faster processors, allowing the computers to work on large data sets at speeds other systems could not approach.

Limiting the number of memory accesses provided the key to extracting high performance from a modern computer. For commodity processors, this meant installing an ever-increasing amount of high-speedcache memoryand using increasingly sophisticated algorithms to avoidcache misses.But the dramatic increase in size of the operating systems and of the applications run on them has generally overwhelmed these cache-processing improvements. Multi-processor systems without NUMA make the problem considerably worse. Now a system can starve several processors at the same time, notably because only one processor can access the computer's memory at a time.[3]

NUMA attempts to address this problem by providing separate memory for each processor, avoiding the performance hit when several processors attempt to address the same memory. For problems involving spread data (common forserversand similar applications), NUMA can improve the performance over a single shared memory by a factor of roughly the number of processors (or separate memory banks).[4]Another approach to addressing this problem is themulti-channel memory architecture,in which a linear increase in the number of memory channels increases the memory access concurrency linearly.[5]

Of course, not all data ends up confined to a single task, which means that more than one processor may require the same data. To handle these cases, NUMA systems include additional hardware or software to move data between memory banks. This operation slows the processors attached to those banks, so the overall speed increase due to NUMA heavily depends on the nature of the running tasks.[4]

Implementations

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AMDimplemented NUMA with itsOpteronprocessor (2003), usingHyperTransport.Intelannounced NUMA compatibility for its x86 andItaniumservers in late 2007 with itsNehalemandTukwilaCPUs.[6]Both Intel CPU families share a commonchipset;the interconnection is called IntelQuickPath Interconnect(QPI), which provides extremely high bandwidth to enable high on-board scalability and was replaced by a new version called IntelUltraPath Interconnectwith the release ofSkylake(2017).[7]

Cache coherent NUMA (ccNUMA)

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Topology of a ccNUMABulldozerserver extracted using hwloc's lstopo tool.
Further information:Directory-based cache coherence

Nearly all CPU architectures use a small amount of very fast non-shared memory known ascacheto exploitlocality of referencein memory accesses. With NUMA, maintainingcache coherenceacross shared memory has a significant overhead. Although simpler to design and build, non-cache-coherent NUMA systems become prohibitively complex to program in the standardvon Neumann architectureprogramming model.[8]

Typically, ccNUMA uses inter-processor communication between cache controllers to keep a consistent memory image when more than one cache stores the same memory location. For this reason, ccNUMA may perform poorly when multiple processors attempt to access the same memory area in rapid succession. Support for NUMA inoperating systemsattempts to reduce the frequency of this kind of access by allocating processors and memory in NUMA-friendly ways and by avoiding scheduling and locking algorithms that make NUMA-unfriendly accesses necessary.[9]

Alternatively, cache coherency protocols such as theMESIF protocolattempt to reduce the communication required to maintain cache coherency.Scalable Coherent Interface(SCI) is anIEEEstandard defining a directory-based cache coherency protocol to avoid scalability limitations found in earlier multiprocessor systems. For example, SCI is used as the basis for the NumaConnect technology.[10][11]

NUMA vs. cluster computing

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One can view NUMA as a tightly coupled form ofcluster computing.The addition ofvirtual memorypaging to a cluster architecture can allow the implementation of NUMA entirely in software. However, the inter-node latency of software-based NUMA remains several orders of magnitude greater (slower) than that of hardware-based NUMA.[2]

Software support

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Since NUMA largely influences memory access performance, certain software optimizations are needed to allow scheduling threads and processes close to their in-memory data.

  • MicrosoftWindows 7andWindows Server 2008 R2added support for NUMA architecture over 64 logical cores.[12]
  • Java 7added support for NUMA-aware memory allocator andgarbage collector.[13]
  • Linux kernel:
    • Version 2.5 provided a basic NUMA support,[14]which was further improved in subsequent kernel releases.
    • Version 3.8 of the Linux kernel brought a new NUMA foundation that allowed development of more efficient NUMA policies in later kernel releases.[15][16]
    • Version 3.13 of the Linux kernel brought numerous policies that aim at putting a process near its memory, together with the handling of cases such as havingmemory pagesshared between processes, or the use of transparenthuge pages;newsysctlsettings allow NUMA balancing to be enabled or disabled, as well as the configuration of various NUMA memory balancing parameters.[17][18][19]
  • OpenSolarismodels NUMA architecture with lgroups.
  • FreeBSDadded support for NUMA architecture in version 9.0.[20]
  • Silicon GraphicsIRIX(discontinued as of 2021) support for ccNUMA architecture over 1240 CPU with Origin server series.

Hardware support

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As of 2011, ccNUMA systems are multiprocessor systems based on theAMD Opteronprocessor, which can be implemented without external logic, and the IntelItanium processor,which requires the chipset to support NUMA. Examples of ccNUMA-enabled chipsets are the SGI Shub (Super hub), the Intel E8870, theHPsx2000 (used in the Integrity and Superdome servers), and those found in NEC Itanium-based systems. Earlier ccNUMA systems such as those fromSilicon Graphicswere based onMIPSprocessors and theDECAlpha 21364(EV7) processor.

See also

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References

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  1. ^This article is based on material taken fromNon-uniform+memory+accessat theFree On-line Dictionary of Computingprior to 1 November 2008 and incorporated under the "relicensing" terms of theGFDL,version 1.3 or later.
  2. ^abNakul Manchanda; Karan Anand (2010-05-04)."Non-Uniform Memory Access (NUMA)"(PDF).New York University. Archived fromthe original(PDF)on 2013-12-28.Retrieved2014-01-27.
  3. ^Sergey Blagodurov; Sergey Zhuravlev; Mohammad Dashti; Alexandra Fedorov (2011-05-02)."A Case for NUMA-aware Contention Management on Multicore Systems"(PDF).Simon Fraser University.Retrieved2014-01-27.
  4. ^abZoltan Majo; Thomas R. Gross (2011)."Memory System Performance in a NUMA Multicore Multiprocessor"(PDF).ACM. Archived fromthe original(PDF)on 2013-06-12.Retrieved2014-01-27.
  5. ^"Intel Dual-Channel DDR Memory Architecture White Paper"(PDF)(Rev. 1.0 ed.). Infineon Technologies North America and Kingston Technology. September 2003. Archived fromthe original(PDF, 1021KB)on 2011-09-29.Retrieved2007-09-06.
  6. ^Intel Corp. (2008). Intel QuickPath Architecture [White paper]. Retrieved fromhttp://www.intel.com/pressroom/archive/reference/whitepaper_QuickPath.pdf
  7. ^Intel Corporation. (September 18th, 2007). Gelsinger Speaks To Intel And High-Tech Industry's Rapid Technology Caden[Press release]. Retrieved fromhttp://www.intel.com/pressroom/archive/releases/2007/20070918corp_b.htm
  8. ^"ccNUMA: Cache Coherent Non-Uniform Memory Access".slideshare.net. 2014.Retrieved2014-01-27.
  9. ^Per Stenstromt; Truman Joe; Anoop Gupta (2002)."Comparative Performance Evaluation of Cache-Coherent NUMA and COMA Architectures"(PDF).ACM.Retrieved2014-01-27.
  10. ^David B. Gustavson (September 1991)."The Scalable Coherent Interface and Related Standards Projects"(PDF).SLAC Publication 5656.Stanford Linear Accelerator Center.Archived(PDF)from the original on 2022-10-09.RetrievedJanuary 27,2014.
  11. ^"The NumaChip enables cache coherent low cost shared memory".Numascale.com. Archived fromthe originalon 2014-01-22.Retrieved2014-01-27.
  12. ^NUMA Support (MSDN)
  13. ^Java HotSpot Virtual Machine Performance Enhancements
  14. ^"Linux Scalability Effort: NUMA Group Homepage".SourceForge.net.2002-11-20.Retrieved2014-02-06.
  15. ^"Linux kernel 3.8, Section 1.8. Automatic NUMA balancing".kernelnewbies.org.2013-02-08.Retrieved2014-02-06.
  16. ^Jonathan Corbet (2012-11-14)."NUMA in a hurry".LWN.net.Retrieved2014-02-06.
  17. ^"Linux kernel 3.13, Section 1.6. Improved performance in NUMA systems".kernelnewbies.org.2014-01-19.Retrieved2014-02-06.
  18. ^"Linux kernel documentation: Documentation/sysctl/kernel.txt".kernel.org.Retrieved2014-02-06.
  19. ^Jonathan Corbet (2013-10-01)."NUMA scheduling progress".LWN.net.Retrieved2014-02-06.
  20. ^"numa(4)".www.freebsd.org.Retrieved2020-12-03.
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