Wikipedia

VIA Nano

"VIA CN" redirects here. "VIA CN" can also mean thatVIA RailusesCNtrackage.

TheVIA Nano(formerlycode-namedVIA Isaiah) is a64-bitCPUforpersonal computers.TheVIA Nanowas released byVIA Technologiesin 2008 after five years of development[1]by its CPU division,Centaur Technology.This new Isaiah 64-bit architecture was designed from scratch, unveiled on 24 January 2008,[2][3][4][5]and launched on 29 May, including low-voltage variants and the Nano brand name.[6]The processor supports a number of VIA-specificx86extensions designed to boost efficiency in low-power appliances.

VIA Nano
General information
Marketed byVIA Technologies
Designed byCentaur Technology
Common manufacturers
Performance
FSBspeeds533 MHz to 1066 MHz
Cache
L1cache64 KiB instruction + 64 KiB data per core
L2 cache1 MiB per core, exclusive
Architecture and classification
Technology node40 nm to 65 nm
MicroarchitectureVIA Isaiah
Instruction setIA-32,x86-64
Extensions
Physical specifications
Cores
  • 1, 2, 4
Package
Products, models, variants
Core name
  • Isaiah (CN)
History
PredecessorVIA C7
VIA Nano 2 Logo

History

edit

UnlikeIntelandAMD,VIA uses two distinct development code names for each of its CPU cores. In this case, the codename 'CN' was used in theUnited Statesby Centaur Technology. Biblical names are used as codes by VIA inTaiwan,and Isaiah was the choice for this particular processor and architecture. It is expected that the VIA Isaiah will be twice as fast in integer performance and four times as fast infloating-pointperformance as the previous-generationVIA Estherat an equivalentclock speed.Power consumption is also expected to be on par with the previous-generation VIA CPUs, withthermal design powerranging from 5 W to 25 W.[7]Being a completely new design, the Isaiah architecture was built with support for features like thex86-64instruction set andx86 virtualizationwhich were unavailable on its predecessors, theVIA C7line, while retaining their encryption extensions. Several independent tests showed that the VIA Nano performs better than the single-coreIntel Atomacross a variety of workloads.[8][9][10]In a 2008Ars Technicatest, a VIA Nano gained significant performance in memory subsystem after its CPUID changed to Intel, hinting at the possibility that the benchmark software only checks the CPUID instead of the actual features supported by the CPU to choose a code path. The benchmark software used had been released before the release of VIA Nano.[11]

On November 3, 2009, VIA launched the Nano 3000 series. VIA claims that these models can offer a 20% performance boost and 20% more energy efficiency than the Nano 1000 and 2000 series.[12]Benchmarks run by VIA claim that a 1.6 GHz 3000-series Nano can outperform the ageing Intel Atom N270 by about 40–54%.[13]The 3000 series adds theSSE4SIMDinstruction set extensions, which were first introduced with 45 nm revisions of theIntelCore 2architecture.

On November 11, 2011, VIA released the VIA Nano X2 Dual-Core Processor with their first ever dual core pico-itx mainboard. The VIA Nano X2 is built on a 40 nm process and supports theSSE4SIMDinstruction set extensions, critical to modern floating point dependent applications.[14]Via claims 30% higher performance in comparison to Intel's Atom with a 50% higher clock.[15]

TheZhaoxinjoint venture processors, released from 2014, are based on the VIA Nano series.

Features

edit
VIA Isaiahfloorplan
  • x86-64instruction set
  • Clock speed from 1 GHz to 2 GHz
  • Bus speed of 533MHzor 800 MHz (1066 MHz for Nano x2)
  • 64 KB data and 64 KB instructionsL1 cacheand 1 MBL2 cacheper core.[16]
  • 65nmmanufacturing process (40 nm for Nano x2)
  • Superscalarout-of-orderinstruction execution
  • Support for MMX, SSE, SSE2, SSE3, SSSE3, and SSE4 instruction set
  • Support forx86 virtualizationwith Intel-compatible implementation (disabled before stepping 3)
  • Support forECC memory
  • Pin-compatible withVIA C7andVIA Eden

Architecture overview

edit
VIA Isaiah Architecturediefloor-plan
Nano X2microarchitecture.
  • Out-of-orderandsuperscalardesign:Providing much better performance than its predecessor, the VIA C7 processor, which was in-order. This puts the Isaiah architecture in line with same year offerings from AMD and Intel.
  • Instructions fusion:Allows the processor to combine multiple instructions into a single one, improving performance and reducing power consumption. This technique, similar to the approach used by the Atom processor, is more efficient than breaking down instructions into smaller units.
  • Improvedbranch prediction:Uses eight predictors in two pipeline stages.
  • CPU cachedesign:An exclusive cache design means that contents of the L1 cache is not duplicated in the L2 cache, providing a larger total cache.
  • Data prefetch:Incorporating new mechanisms for data-prefetch, including both the loading of a special 64-line cache before loading the L2 cache and a direct load to the L1 cache.
  • Memoryaccess:Merges smaller stores into larger load data.
  • Execution units:Seven execution units are available, that allows up to seven micro-ops being executed per clock.
    • Two integer units (ALU1 and ALU2)
      • ALU1 is feature complete, while ALU2 lacks some low usage instructions and therefore is more suited for tasks like address calculations.
    • Two store units, one for Address Store and one for Data Store according toVIA.
    • One load unit
    • Two media units (MEDIA-A and MEDIA-B) with a128-bitwidedatapath,supporting 4 single precision or 2 double-precision operations.Media computationrefers to the use of the two media units.
      • MEDIA-A executes floating-point "add" instructions (2-clock latency forsingle-precisionanddouble-precision), integer SIMD, encryption, divide and square root.
      • MEDIA-B executes floating-point "multiply" instructions (2-clock latency for single-precision, 3-clock latency for double-precision).
      • Because of the parallelism introduced with the two media units, media computation can provide four "add" and four "multiply" instructions per clock.
    • A new implementation of FP-addition with the lowest clock-latency for a x86 processor so far.
    • Almost all integerSIMDinstructions execute in one clock.
    • ImplementsMMX,SSE,SSE2,SSE3,SSSE3multimedia instruction sets
    • ImplementsSSE4.1multimedia instruction set (VIA Nano 3000 series)
    • ImplementsSSE4.1multimedia instruction set (VIA Nano x2 series)
  • Power Management:Besides requiring very low power, many new features are included.
    • Includes a new C6 power state (Caches are flushed, internal state saved, and core voltage is turned off).
    • Adaptive P-State Control:Transition between performance and voltage states without stopping execution.
    • Adaptive Overclocking:Automatic overclocking if there is low temperature in the processor core.
    • Adaptive Thermal Limit:Adjusting of the processor to maintain a user predefined temperature.
  • Encryption:Includes the VIA PadLock engine

See also

edit

References

edit
  1. ^"VIA to launch new processor architecture in 1Q08".DigiTimes.Archivedfrom the original on 3 December 2008.Retrieved25 July2007.
  2. ^Stokes, Jon (23 January 2008)."Isaiah revealed: VIA's new low-power architecture".Ars Technica.Archivedfrom the original on 27 January 2008.Retrieved24 January2008.
  3. ^Bennett, Kyle (24 January 2008)."VIA's New Centaur Designed Isaiah CPU Architecture".[H]ard|OCP.Archived fromthe originalon 19 July 2011.Retrieved24 January2008.
  4. ^"Via launches 64-bit architecture".LinuxDevices.com.23 January 2008. Archived fromthe originalon 2013-01-03.Retrieved24 January2008.
  5. ^Wasson, Scott (24 January 2008)."A look at VIA's next-gen Isaiah x86 CPU architecture".The Tech Report.Archivedfrom the original on 26 January 2008.Retrieved24 January2008.
  6. ^"VIA Launches VIA Nano Processor Family"(Press release).VIA.29 May 2008.Archivedfrom the original on 3 February 2019.Retrieved29 May2008.
  7. ^"VIA Isaiah Architecture Introduction"(PDF).VIA.23 January 2008. Archived fromthe original(PDF)on 14 June 2011.Retrieved28 May2008.
  8. ^Bennett, Kyle (29 July 2008)."Intel Atom vs. VIA Nano".[H]ard|OCP.Archived fromthe originalon 19 February 2012.
  9. ^Chiappetta, Marco (29 July 2008)."VIA Nano L2100 vs. Intel Atom 230: Head to Head".HotHardware.Archivedfrom the original on 22 July 2011.Retrieved18 January2009.
  10. ^Shrout, Ryan (29 July 2008)."VIA Nano and Intel Atom Review – Battle of the Tiny CPUs".PC Perspective.Archived fromthe originalon 13 January 2010.Retrieved18 January2009.
  11. ^Hruska, Joel (29 July 2008)."Low-end grudge match: Nano vs. Atom".Ars Technica.Archivedfrom the original on 20 January 2012.Retrieved15 June2017.
  12. ^"VIA Introduces New VIA Nano 3000 Series Processors"(Press release).VIA.3 November 2009. Archived fromthe originalon 22 January 2013.
  13. ^"VIA Nano Processor".VIA.Archivedfrom the original on 2008-05-30.Retrieved2008-05-30.
  14. ^"VIA Releases New Nano X2 Dual-Core Processor".Tom's Hardware.Archivedfrom the original on 2022-01-25.Retrieved2013-10-15.
  15. ^"VIA Nano x2 Processor SPECfp2000 Benchmarks".VIA.Archived fromthe originalon 2014-02-07.
  16. ^"The VIA Isaiah Architecture - VIA Technologies, Inc".2013-05-29. Archived fromthe originalon 2013-05-29.Retrieved2020-04-10.
edit
Wikimedia Commons has media related toVIA Nano.

Press

edit
Retrieved from "https://en.wikipedia.org/w/index.php?title=VIA_Nano&oldid=1244090680"