x86

This article is about the Intel microprocessor architecture in general. For the 32-bit generation of this architecture that is also referred to as "x86", seeIA-32.

x86(also known as80x86or the8086 family) is a family ofcomplex instruction set computer(CISC)instruction set architecturesinitially developed byIntelbased on the8086microprocessor and its 8-bit-external-bus variant, the8088.The 8086 was introduced in 1978 as a fully16-bitextension of8-bitIntel's8080microprocessor, withmemory segmentationas a solution for addressing more memory than can be covered by a plain 16-bit address. The term "x86" came into being because the names of several successors to Intel's 8086 processor end in "86", including the80186,80286,80386and80486.Colloquially, their names were "186", "286", "386" and "486".

x86

Designer	Intel,AMD
Bits	16-bit,32-bitand64-bit
Introduced	1978 (16-bit), 1985 (32-bit), 2003 (64-bit)
Design	CISC
Type	Register–memory
Encoding	Variable (1 to 15 bytes)
Branching	Condition code
Endianness	Little
Page size	8086–i286:None i386,i486:4 KB pages P5Pentium:added 4 MB pages (LegacyPAE:4 KB→2 MB) x86-64:added 1 GB pages
Extensions	x87,IA-32,x86-64,X86S,MMX,3DNow!,SSE,MCA,ACPI,SSE2,NX bit,SMT,SSE3,SSSE3,SSE4,SSE4.2,AES-NI,CLMUL,SM3,SM4,RDRAND,SHA,MPX,SME,SGX,XOP,F16C,ADX,BMI,FMA,AVX,AVX2,AVX-VNNI,AVX512,AVX10,AMX,VT-x,VT-d,AMD-V,AMD-Vi,TSX,ASF,TXT,APX
Open	Partly. For some advanced features, x86 may require license from Intel; x86-64 may require an additional license from AMD. ThePentium Proprocessor (andNetBurst) has been on the market for more than 21 yearsand so cannot be subject to patent claims. Thei686subset of the x86 architecture is therefore fully open. TheOpteron1000 series processors have been on the market for more than 21 yearsand so cannot be subject to patent claims. TheAMD K8subset of the x86 architecture is therefore fully open.
Registers
General-purpose	16-bit: 6 semi-dedicated registers, BP and SP are not general-purpose 32-bit: 8 GPRs, including EBP and ESP 64-bit: 16 GPRs, including RBP and RSP
Floating point	16-bit: optional separatex87FPU 32-bit: optional separate or integratedx87FPU, integratedSSEunits in later processors 64-bit: integratedx87andSSE2units, later implementations extended toAVX2andAVX512

The x86 architectures were based on the Intel 8086 microprocessor chip, initially released in 1978.

Intel Core 2 Duo, an example of an x86-compatible, 64-bit multicore processor

AMD Athlon (early version), a technically different but fully compatible x86 implementation

The term is not synonymous withIBM PC compatibility,as this implies a multitude of othercomputer hardware.Embedded systemsand general-purpose computers used x86 chipsbefore the PC-compatible market started,some of them before theIBM PC(1981) debut.

As of June 2022,mostdesktopandlaptopcomputers sold are based on the x86 architecture family,while mobile categories such assmartphonesortabletsare dominated byARM.At the high end, x86 continues to dominate computation-intensiveworkstationandcloud computingsegments.

Overview

In the 1980s and early 1990s, when the8088and80286were still in common use, the term x86 usually represented any 8086-compatible CPU. Today, however, x86 usually implies binary compatibility with the32-bitinstruction setof the80386.This is due to the fact that this instruction set has become something of a lowest common denominator for many modern operating systems and also probably because the term became common after the introduction of the 80386 in 1985.

A few years after the introduction of the 8086 and 8088, Intel added some complexity to its naming scheme and terminology as the "iAPX" of the ambitious but ill-fatedIntel iAPX 432processor was tried on the more successful 8086 family of chips,applied as a kind of system-level prefix. An 8086 system, includingcoprocessorssuch as8087and8089,and simpler Intel-specific system chips,was thereby described as an iAPX 86 system.There were also termsiRMX(for operating systems),iSBC(for single-board computers), andiSBX(for multimodule boards based on the 8086-architecture), all together under the headingMicrosystem 80.However, this naming scheme was quite temporary, lasting for a few years during the early 1980s.

Although the 8086 was primarily developed forembedded systemsand small multi-user or single-user computers, largely as a response to the successful 8080-compatibleZilog Z80,the x86 line soon grew in features and processing power. Today, x86 is ubiquitous in both stationary and portable personal computers, and is also used inmidrange computers,workstations,servers, and most newsupercomputerclustersof theTOP500list. A large amount ofsoftware,including a large list ofx86 operating systemsare using x86-based hardware.

Modern x86 is relatively uncommon inembedded systems,however, and smalllow powerapplications (using tiny batteries), and low-cost microprocessor markets, such ashome appliancesand toys, lack significant x86 presence.Simple 8- and 16-bit based architectures are common here, as well as simpler RISC architectures likeRISC-V,although the x86-compatibleVIA C7,VIA Nano,AMD'sGeode,Athlon NeoandIntel Atomare examples of 32- and64-bitdesigns used in some relatively low-power and low-cost segments.

There have been several attempts, including by Intel, to end the market dominance of the "inelegant" x86 architecture designed directly from the first simple 8-bit microprocessors. Examples of this are theiAPX 432(a project originally named theIntel 8800), theIntel 960,Intel 860and the Intel/Hewlett-PackardItaniumarchitecture. However, the continuous refinement of x86microarchitectures,circuitryandsemiconductor manufacturingwould make it hard to replace x86 in many segments. AMD's 64-bit extension of x86 (which Intel eventually responded to with a compatible design)and the scalability of x86 chips in the form of modern multi-core CPUs, is underlining x86 as an example of how continuous refinement of established industry standards can resist the competition from completely new architectures.

Chronology

The table below lists processor models and model series implementing various architectures in the x86 family, in chronological order. Each line item is characterized by significantly improved or commercially successful processor microarchitecture designs.

Chronology of x86 processors

Era		Introduction	Prominent CPU models	Address space			Notable features
				Linear	Virtual	Physical
x86-16	1st	1978	Intel 8086,Intel 8088(1979)	16-bit	NA	20-bit	16-bitISA,IBM PC(8088),IBM PC/XT(8088)
		1982	Intel 80186,Intel 80188 NEC V20/V30 (1983)				8086-2 ISA, embedded (80186/80188)
	2nd		Intel 80286and clones		30-bit	24-bit	protected mode,IBM PC/XT 286,IBM PC/AT
IA-32	3rd	1985	Intel 80386,AMD Am386(1991)	32-bit	46-bit	32-bit	32-bitISA,paging,IBM PS/2
	4th(pipelining, cache)	1989	Intel 80486 CyrixCx486S,DLC(1992) AMD Am486(1993),Am5x86(1995)				pipelining,on-diex87FPU(486DX), on-diecache
	5th (Superscalar)	1993	IntelPentium,Pentium MMX(1996)				Superscalar,64-bitdatabus,faster FPU,MMX(Pentium MMX),APIC,SMP
		1994	NexGenNx586 AMD5k86/K5(1996)				Discrete microarchitecture (μ-optranslation)
		1995	Cyrix Cx5x86 Cyrix 6x86/MX (1997)/MII(1998)				dynamic execution
	6th (PAE,μ-op translation)	1995	IntelPentium Pro			36-bit (PAE)	μ-op translation, conditional move instructions,dynamic execution,speculative execution,3-way x86 superscalar, superscalar FPU,PAE,on-chipL2 cache
		1997	IntelPentium II,Pentium III(1999) Celeron(1998),Xeon(1998)				on-package (Pentium II) or on-die (Celeron) L2 Cache,SSE(Pentium III),Slot 1,Socket 370orSlot 2(Xeon)
		1997	AMD K6/K6-2(1998)/K6-III(1999)			32-bit	3DNow!,3-level cache system (K6-III)
	Enhanced Platform	1999	AMDAthlon Athlon XP/MP(2001) Duron(2000) Sempron(2004)			36-bit	MMX+, 3DNow!+, double-pumped bus,Slot AorSocket A
		2000	Transmeta Crusoe			32-bit	CMSpowered x86 platform processor,VLIW-128 core, on-die memory controller, on-die PCI bridge logic
			IntelPentium 4			36-bit	SSE2,HTT(Northwood), NetBurst, quad-pumped bus, Trace Cache,Socket 478
		2003	IntelPentium M Intel Core(2006) Pentium Dual-Core(2007)				μ-op fusion,XD bit(Dothan) (Intel Core "Yonah" )
			Transmeta Efficeon				CMS6.0.4,VLIW-256,NX bit,HT
IA-64	64-bit Transition 1999–2005	2001	IntelItanium(2001–2017)	52-bit			64-bitEPICarchitecture, 128-bit VLIW instruction bundle, on-die hardware IA-32 H/W enabling x86 OSes & x86 applications (early generations), software IA-32 EL enabling x86 applications (Itanium 2), Itanium register files are remapped to x86 registers
x86-64	64-bit Extended since 2001	x86-64 is the 64-bit extended architecture of x86, its Legacy Mode preserves the entire and unaltered x86 architecture. The native architecture of x86-64 processors: residing in the 64-bit Mode, lacks of access mode in segmentation, presenting 64-bit architectural-permit linear address space; an adapted IA-32 architecture residing in the Compatibility Mode alongside 64-bit Mode is provided to support most x86 applications
		2003	Athlon 64/FX/X2(2005),Opteron Sempron(2004)/X2(2008) Turion 64(2005)/X2(2006)	40-bit			AMD64(except some Sempron processors presented as purely x86 processors), on-die memory controller,HyperTransport,on-die dual-core (X2),AMD-V(Athlon 64 Orleans),Socket 754/939/940orAM2
		2004	Pentium 4(Prescott) Celeron D,Pentium D(2005)	36-bit			EM64T(enabled on selected models of Pentium 4 and Celeron D),SSE3,2nd gen. NetBurst pipelining, dual-core (on-die: Pentium D 8xx, on-chip: Pentium D 9xx),Intel VT(Pentium 4 6x2), socketLGA 775
		2006	Intel Core 2 Pentium Dual-Core(2007) Celeron Dual-Core(2008)				Intel 64(<<== EM64T),SSSE3(65 nm), wide dynamic execution, μ-op fusion, macro-op fusion in 16-bit and 32-bit mode,on-chip quad-core(Core 2 Quad), Smart Shared L2 Cache (Intel Core 2 "Merom" )
		2007	AMD Phenom/II(2008) Athlon II(2009) Turion II(2009)	48-bit			Monolithic quad-core (X4)/triple-core (X3),SSE4a,Rapid Virtualization Indexing(RVI), HyperTransport 3,AM2+orAM3
		2008	Intel Core 2(45 nm)	40-bit			SSE4.1
			Intel Atom				netbook or low power smart device processor, P54C core reused
			IntelCore i7 Core i5(2009) Core i3(2010)				QuickPath, on-chip GMCH (Clarkdale),SSE4.2,Extended Page Tables(EPT) for virtualization, macro-op fusion in 64-bit mode,(Intel Xeon "Bloomfield" with Nehalem microarchitecture)
			VIA Nano				hardware-based encryption;adaptivepower management
		2010	AMD FX	48-bit			octa-core, CMT(Clustered Multi-Thread), FMA, OpenCL, AM3+
		2011	AMD APU A and E Series (Llano)	40-bit			on-die GPGPU, PCI Express 2.0,Socket FM1
			AMD APU C, E and Z Series (Bobcat)	36-bit			low power smart device APU
			Intel Core i3,Core i5andCore i7 (Sandy Bridge/Ivy Bridge)				Internal Ring connection, decoded μ-op cache,LGA 1155socket
		2012	AMD APU A Series (Bulldozer, Trinityand later)	48-bit			AVX,Bulldozer based APU,Socket FM2orSocket FM2+
			IntelXeon Phi(Knights Corner)				PCI-E add-on card coprocessor for XEON based system, Manycore Chip, In-orderP54C,very wide VPU (512-bit SSE), LRBni instructions (8× 64-bit)
		2013	AMDJaguar (Athlon, Sempron)				SoC,game console and low power smart device processor
			IntelSilvermont (Atom, Celeron, Pentium)	36-bit			SoC,low/ultra-low power smart device processor
			Intel Core i3,Core i5andCore i7(Haswell/Broadwell)	39-bit			AVX2,FMA3,TSX,BMI1, and BMI2instructions,LGA 1150socket
		2015	IntelBroadwell-U (Intel Core i3,Core i5,Core i7,Core M,Pentium,Celeron)				SoC, on-chip Broadwell-U PCH-LP (Multi-chip module)
		2015–2020	IntelSkylake/Kaby Lake/Cannon Lake/Coffee Lake/Rocket Lake (Intel Pentium/Celeron Gold,Core i3,Core i5,Core i7,Core i9)	46-bit			AVX-512 (restricted to Cannon Lake-U and workstation/server variants of Skylake)
		2016	IntelXeon Phi(Knights Landing)	48-bit			Manycore CPU and coprocessor for Xeon systems, Airmont (Atom) based core
		2016	AMDBristol Ridge (AMD (Pro) A6/A8/A10/A12)				Integrated FCH on die, SoC, AM4 socket
		2017	AMDRyzenSeries/AMDEpycSeries				AMD's implementation of SMT, on-chip multiple dies
		2017	Zhaoxin WuDaoKou (KX-5000, KH-20000)				Zhaoxin's first brand new x86-64 architecture
		2018–2021	IntelSunny Cove(Ice Lake-U and Y),Cypress Cove(Rocket Lake)	57-bit			Intel's first implementation of AVX-512 for the consumer segment. Addition of Vector Neural Network Instructions (VNNI)
		2019	AMDMatisse	48-bit			Multiple Chip Module design with I/O die separate from CPU die(s), Support for PCIe Gen4
		2020	IntelWillow Cove(Tiger Lake-Y/U/H)	57-bit			Dual ring interconnect architecture, updated Gaussian Neural Accelerator (GNA2), new AVX-512 Vector Intersection Instructions, addition of Control-Flow Enforcement Technology (CET)
		2021	IntelAlder Lake				Hybrid design with performance (Golden Cove) and efficiency cores (Gracemont), support for PCIe Gen5 and DDR5, updated Gaussian Neural Accelerator (GNA3). AVX-512 not officially supported
		2022	AMDVermeer(5800X3D)	48-bit			X3D chips have an additional 64MB 3D vertically stacked L3 cache (3D V-Cache) for up to 96MB L3 Cache
		2022	AMDRaphael				AMD's first implementation of AVX-512 for the consumer segment, iGPU now standard on Ryzen CPU's with 2RDNA 2compute cores
Era		Introduction	Prominent CPU models	Address space			Notable features

History

Designers and manufacturers

Am386,released by AMD in 1991

Further information:List of former IA-32 compatible processor manufacturers

At various times, companies such asIBM,VIA,NEC,AMD,TI,STM,Fujitsu,OKI,Siemens,Cyrix,Intersil,C&T,NexGen,UMC,andDM&Pstarted to design or manufacturex86processors(CPUs) intended for personal computers and embedded systems. Other companies that designed or manufactured x86 orx87processors includeITT Corporation,National Semiconductor,ULSI System Technology, andWeitek.

Such x86 implementations were seldom simple copies but often employed different internalmicroarchitecturesand different solutions at the electronic and physical levels. Quite naturally, early compatible microprocessors were 16-bit, while 32-bit designs were developed much later. For thepersonal computermarket, real quantities started to appear around 1990 withi386andi486compatible processors, often named similarly to Intel's original chips.

After the fullypipelinedi486,in 1993Intelintroduced thePentiumbrand name (which, unlike numbers, could betrademarked) for their new set ofsuperscalarx86 designs. With the x86 naming scheme now legally cleared, other x86 vendors had to choose different names for their x86-compatible products, and initially some chose to continue with variations of the numbering scheme:IBMpartnered withCyrixto produce the5x86and then the very efficient6x86(M1) and6x86MX (MII) lines of Cyrix designs, which were the first x86 microprocessors implementingregister renamingto enablespeculative execution.

AMD meanwhile designed and manufactured the advanced but delayed5k86(K5), which, internally, was closely based on AMD's earlier29KRISCdesign; similar toNexGen'sNx586,it used a strategy such that dedicated pipeline stages decode x86 instructions into uniform and easily handledmicro-operations,a method that has remained the basis for most x86 designs to this day.

Some early versions of these microprocessors had heat dissipation problems. The 6x86 was also affected by a few minor compatibility problems, theNx586lacked afloating-point unit(FPU) and (the then crucial) pin-compatibility, while theK5had somewhat disappointing performance when it was (eventually) introduced.

Customer ignorance of alternatives to the Pentium series further contributed to these designs being comparatively unsuccessful, despite the fact that theK5had very good Pentium compatibility and the6x86was significantly faster than the Pentium on integer code.AMDlater managed to grow into a serious contender with theK6set of processors, which gave way to the very successfulAthlonandOpteron.

There were also other contenders, such asCentaur Technology(formerlyIDT),Rise Technology,andTransmeta.VIA Technologies' energy efficientC3andC7processors, which were designed by theCentaurcompany, were sold for many years following their release in 2005. Centaur's 2008 design, theVIA Nano,was their first processor withsuperscalarandspeculative execution.It was introduced at about the same time (in 2008) as Intel introduced theIntel Atom,its first "in-order" processor after theP5Pentium.

Many additions and extensions have been added to the original x86 instruction set over the years, almost consistently with fullbackward compatibility.The architecture family has been implemented in processors from Intel,Cyrix,AMD,VIA Technologiesand many other companies; there are also open implementations, such as the Zet SoC platform (currently inactive).Nevertheless, of those, only Intel, AMD, VIA Technologies, andDM&P Electronicshold x86 architectural licenses, and from these, only the first two actively produce modern 64-bit designs, leading to what has been called a "duopoly" of Intel and AMD in x86 processors.

However, in 2014 the Shanghai-based Chinese companyZhaoxin,a joint venture between a Chinese company and VIA Technologies, began designing VIA based x86 processors for desktops and laptops. The release of its newest "7" familyof x86 processors (e.g. KX-7000), which are not quite as fast as AMD or Intel chips but are still state of the art,had been planned for 2021; as of March 2022 the release had not taken place, however.

From 16-bit and 32-bit to 64-bit architecture

Theinstruction set architecturehas twice been extended to a largerwordsize. In 1985, Intel released the 32-bit 80386 (later known as i386) which gradually replaced the earlier 16-bit chips in computers (although typically not inembedded systems) during the following years; this extended programming model was originally referred to asthe i386 architecture(like its first implementation) but Intel later dubbed itIA-32when introducing its (unrelated)IA-64architecture.

In 1999–2003,AMDextended this 32-bit architecture to 64 bits and referred to it asx86-64in early documents and later asAMD64.Intel soon adopted AMD's architectural extensions under the name IA-32e, later using the name EM64T and finally using Intel 64.MicrosoftandSun Microsystems/Oraclealso use term "x64", while manyLinux distributions,and theBSDsalso use the "amd64" term. Microsoft Windows, for example, designates its 32-bit versions as "x86" and 64-bit versions as "x64", while installation files of 64-bit Windows versions are required to be placed into a directory called "AMD64".

In 2023, Intel proposed a major change to the architecture referred to asX86S(formerly known as X86-S). The S in X86S stands for "simplification", which aims to remove support for legacy execution modes and instructions. A processor implementing this proposal would start execution directly inlong modeand would only support 64-bit operating systems. 32-bit code would only be supported for user applications running in ring 3, and would use the same simplified segmentation as long mode.

Basic properties of the architecture

The x86 architecture is a variable instruction length, primarily "CISC"design with emphasis onbackward compatibility.The instruction set is not typical CISC, however, but basically an extended version of the simple eight-bit8008and8080architectures. Byte-addressing is enabled and words are stored in memory withlittle-endianbyte order. Memory access to unaligned addresses is allowed for almost all instructions. The largest native size forintegerarithmetic and memory addresses (oroffsets) is 16, 32 or 64 bits depending on architecture generation (newer processors include direct support for smaller integers as well). Multiple scalar values can be handled simultaneously via the SIMD unit present in later generations, as described below.Immediate addressing offsets and immediate data may be expressed as 8-bit quantities for the frequently occurring cases or contexts where a −128..127 range is enough. Typical instructions are therefore 2 or 3 bytes in length (although some are much longer, and some are single-byte).

To further conserve encoding space, most registers are expressed inopcodesusing three or four bits, the latter via an opcode prefix in 64-bit mode, while at most one operand to an instruction can be a memory location.However, this memory operand may also be the destination (or a combined source and destination), while the other operand, the source, can be either register or immediate. Among other factors, this contributes to a code size that rivals eight-bit machines and enables efficient use of instruction cache memory. The relatively small number of general registers (also inherited from its 8-bit ancestors) has made register-relative addressing (using small immediate offsets) an important method of accessing operands, especially on the stack. Much work has therefore been invested in making such accesses as fast as register accesses—i.e., a one cycle instruction throughput, in most circumstances where the accessed data is available in the top-level cache.

Floating point and SIMD

A dedicatedfloating-point processorwith 80-bit internal registers, the8087,was developed for the original8086.This microprocessor subsequently developed into the extended80387,and later processors incorporated abackward compatibleversion of this functionality on the same microprocessor as the main processor. In addition to this, modern x86 designs also contain aSIMD-unit (seeSSEbelow) where instructions can work in parallel on (one or two) 128-bit words, each containing two or fourfloating-point numbers(each 64 or 32 bits wide respectively), or alternatively, 2, 4, 8 or 16 integers (each 64, 32, 16 or 8 bits wide respectively).

The presence of wide SIMD registers means that existing x86 processors can load or store up to 128 bits of memory data in a single instruction and also perform bitwise operations (although not integer arithmetic) on full 128-bits quantities in parallel. Intel'sSandy Bridgeprocessors added theAdvanced Vector Extensions(AVX) instructions, widening the SIMD registers to 256 bits. The Intel Initial Many Core Instructions implemented by the Knights CornerXeon Phiprocessors, and theAVX-512instructions implemented by the Knights Landing Xeon Phi processors and bySkylake-Xprocessors, use 512-bit wide SIMD registers.

Current implementations

Duringexecution,current x86 processors employ a few extra decoding steps to split most instructions into smaller pieces called micro-operations. These are then handed to acontrol unitthat buffers and schedules them in compliance with x86-semantics so that they can be executed, partly in parallel, by one of several (more or less specialized)execution units.These modern x86 designs are thuspipelined,superscalar,and also capable ofout of orderandspeculative execution(viabranch prediction,register renaming,andmemory dependence prediction), which means they may execute multiple (partial or complete) x86 instructions simultaneously, and not necessarily in the same order as given in the instruction stream. Some Intel CPUs (Xeon Foster MP,somePentium 4,and someNehalemand laterIntel Coreprocessors) and AMD CPUs (starting fromZen) are also capable ofsimultaneous multithreadingwith twothreadspercore(Xeon Phihas four threads per core). Some Intel CPUs supporttransactional memory(TSX).

When introduced, in the mid-1990s, this method was sometimes referred to as a "RISC core" or as "RISC translation", partly for marketing reasons, but also because these micro-operations share some properties with certain types of RISC instructions. However, traditionalmicrocode(used since the 1950s) also inherently shares many of the same properties; the new method differs mainly in that the translation to micro-operations now occurs asynchronously. Not having to synchronize the execution units with the decode steps opens up possibilities for more analysis of the (buffered) code stream, and therefore permits detection of operations that can be performed in parallel, simultaneously feeding more than one execution unit.

The latest processors also do the opposite when appropriate; they combine certain x86 sequences (such as a compare followed by a conditional jump) into a more complex micro-op which fits the execution model better and thus can be executed faster or with fewer machine resources involved.

Another way to try to improve performance is to cache the decoded micro-operations, so the processor can directly access the decoded micro-operations from a special cache, instead of decoding them again. Intel followed this approach with the Execution Trace Cache feature in theirNetBurstmicroarchitecture (for Pentium 4 processors) and later in the Decoded Stream Buffer (for Core-branded processors since Sandy Bridge).

Transmetaused a completely different method in theirCrusoex86 compatible CPUs. They usedjust-in-timetranslation to convert x86 instructions to the CPU's nativeVLIWinstruction set. Transmeta argued that their approach allows for more power efficient designs since the CPU can forgo the complicated decode step of more traditional x86 implementations.

Addressing modes

Addressing modesfor 16-bit processor modes can be summarized by the formula:

${\begin{matrix}{\mathtt {CS}}:\\{\mathtt {DS}}:\\{\mathtt {SS}}:\\{\mathtt {ES}}:\end{matrix}}\ \ {\begin{pmatrix}\\{\begin{bmatrix}{\mathtt {BX}}\\{\mathtt {BP}}\end{bmatrix}}+{\begin{bmatrix}{\mathtt {SI}}\\{\mathtt {DI}}\end{bmatrix}}\\\\\end{pmatrix}}+{\rm {displacement}}$

Addressing modes for 32-bit x86 processor modescan be summarized by the formula:

${\begin{matrix}{\mathtt {CS}}:\\{\mathtt {DS}}:\\{\mathtt {SS}}:\\{\mathtt {ES}}:\\{\mathtt {FS}}:\\{\mathtt {GS}}:\end{matrix}}\ \ {\begin{bmatrix}{\mathtt {EAX}}\\{\mathtt {EBX}}\\{\mathtt {ECX}}\\{\mathtt {EDX}}\\{\mathtt {ESP}}\\{\mathtt {EBP}}\\{\mathtt {ESI}}\\{\mathtt {EDI}}\end{bmatrix}}+{\begin{pmatrix}\\{\begin{bmatrix}{\mathtt {EAX}}\\{\mathtt {EBX}}\\{\mathtt {ECX}}\\{\mathtt {EDX}}\\{\mathtt {EBP}}\\{\mathtt {ESI}}\\{\mathtt {EDI}}\end{bmatrix}}*{\begin{bmatrix}1\\2\\4\\8\end{bmatrix}}\\\\\end{pmatrix}}+{\rm {displacement}}$

Addressing modes for the 64-bit processor mode can be summarized by the formula:

${\begin{Bmatrix}\\{\begin{matrix}{\mathtt {FS}}:\\{\mathtt {GS}}:\end{matrix}}\ \ {\begin{bmatrix}\vdots \\{\mathtt {GPR}}\\\vdots \end{bmatrix}}+{\begin{pmatrix}\\{\begin{bmatrix}\vdots \\{\mathtt {GPR}}\\\vdots \\\end{bmatrix}}*{\begin{bmatrix}1\\2\\4\\8\end{bmatrix}}\\\\\end{pmatrix}}\\\\\hline \\{\begin{matrix}{\mathtt {RIP}}\end{matrix}}\\\\\end{Bmatrix}}+{\rm {displacement}}$

Instruction relative addressing in 64-bit code (RIP + displacement, where RIP is theinstruction pointer register) simplifies the implementation ofposition-independent code(as used inshared librariesin some operating systems).

The 8086 had64 KBof eight-bit (or alternatively32 K-word of 16-bit)I/Ospace, and a64 KB(one segment)stackin memory supported bycomputer hardware.Only words (two bytes) can be pushed to the stack. The stack grows toward numerically lower addresses, withSS:SPpointing to the most recently pushed item. There are 256interrupts,which can be invoked by both hardware and software. The interrupts can cascade, using the stack to store thereturn address.

x86 registers

For a description of the general notion of a CPU register, seeProcessor register.

16-bit

The originalIntel 8086and8088have fourteen 16-bitregisters. Four of them (AX, BX, CX, DX) are general-purpose registers (GPRs), although each may have an additional purpose; for example, only CX can be used as a counter with the loop instruction. Each can be accessed as two separate bytes (thus BX's high byte can be accessed as BH and low byte as BL). Two pointer registers have special roles: SP (stack pointer) points to the "top" of thestack,and BP (base pointer) is often used to point at some other place in the stack, typically above the local variables (seeframe pointer). The registers SI, DI, BX and BP areaddress registers,and may also be used for array indexing.

One of four possible 'segment registers' (CS, DS, SS and ES) is used to form a memory address. In the original 8086 / 8088 / 80186 / 80188 every address was built from a segment register and one of the general purpose registers. For example ds:si is the notation for an address formed as [16 * ds + si] to allow 20-bit addressing rather than 16 bits, although this changed in later processors. At that time only certain combinations were supported.

TheFLAGS registercontainsflagssuch ascarry flag,overflow flagandzero flag.Finally, the instruction pointer (IP) points to the next instruction that will be fetched from memory and then executed; this register cannot be directly accessed (read or written) by a program.

TheIntel 80186and80188are essentially an upgraded 8086 or 8088 CPU, respectively, with on-chip peripherals added, and they have the same CPU registers as the 8086 and 8088 (in addition to interface registers for the peripherals).

The 8086, 8088, 80186, and 80188 can use an optional floating-point coprocessor, the8087.The 8087 appears to the programmer as part of the CPU and adds eight 80-bit wide registers, st(0) to st(7), each of which can hold numeric data in one of seven formats: 32-, 64-, or 80-bit floating point, 16-, 32-, or 64-bit (binary) integer, and 80-bit packed decimal integer.It also has its own 16-bit status register accessible through thefstswinstruction, and it is common to simply use some of its bits for branching by copying it into the normal FLAGS.

In theIntel 80286,to supportprotected mode,three special registers hold descriptor table addresses (GDTR, LDTR,IDTR), and a fourth task register (TR) is used for task switching. The80287is the floating-point coprocessor for the 80286 and has the same registers as the 8087 with the same data formats.

32-bit

Registers available in the x86-64 instruction set

With the advent of the 32-bit80386processor, the 16-bit general-purpose registers, base registers, index registers, instruction pointer, andFLAGS register,but not the segment registers, were expanded to 32 bits. The nomenclature represented this by prefixing an "E"(for" extended ") to the register names inx86 assembly language.Thus, the AX register corresponds to the lower 16 bits of the new 32-bit EAX register, SI corresponds to the lower 16 bits of ESI, and so on. The general-purpose registers, base registers, and index registers can all be used as the base in addressing modes, and all of those registers except for the stack pointer can be used as the index in addressing modes.

Two new segment registers (FS and GS) were added. With a greater number of registers, instructions and operands, themachine codeformat was expanded. To provide backward compatibility, segments with executable code can be marked as containing either 16-bit or 32-bit instructions. Special prefixes allow inclusion of 32-bit instructions in a 16-bit segment or vice versa.

The 80386 had an optional floating-point coprocessor, the80387;it had eight 80-bit wide registers: st(0) to st(7),like the 8087 and 80287. The 80386 could also use an 80287 coprocessor.With the80486and all subsequent x86 models, the floating-point processing unit (FPU) is integrated on-chip.

ThePentium MMXadded eight 64-bitMMXinteger vector registers (MM0 to MM7, which share lower bits with the 80-bit-wide FPU stack).With thePentium III,Intel added a 32-bitStreaming SIMD Extensions(SSE) control/status register (MXCSR) and eight 128-bit SSE floating-point registers (XMM0 to XMM7).

64-bit

Further information:x86-64

Starting with theAMD Opteronprocessor, the x86 architecture extended the 32-bit registers into 64-bit registers in a way similar to how the 16 to 32-bit extension took place. AnR-prefix (for "register" ) identifies the 64-bit registers (RAX, RBX, RCX, RDX, RSI, RDI, RBP, RSP, RFLAGS, RIP), and eight additional 64-bit general registers (R8–R15) were also introduced in the creation ofx86-64.Also, eight more SSE vector registers (XMM8–XMM15) were added. However, these extensions are only usable in 64-bit mode, which is one of the two modes only available inlong mode.The addressing modes were not dramatically changed from 32-bit mode, except that addressing was extended to 64 bits, virtual addresses are now sign extended to 64 bits (in order to disallow mode bits in virtual addresses), and other selector details were dramatically reduced. In addition, an addressing mode was added to allow memory references relative to RIP (theinstruction pointer), to ease the implementation ofposition-independent code,used in shared libraries in some operating systems.

128-bit

See also:Streaming SIMD Extensions § Registers

SIMD registers XMM0–XMM15 (XMM0–XMM31 whenAVX-512is supported).

256-bit

See also:Advanced Vector Extensions § New features

SIMD registers YMM0–YMM15 (YMM0–YMM31 whenAVX-512is supported). Lower half of each of the YMM registers maps onto the corresponding XMM register.

512-bit

See also:Advanced Vector Extensions § AVX-512

SIMD registers ZMM0–ZMM31. Lower half of each of the ZMM registers maps onto the corresponding YMM register.

Miscellaneous/special purpose

x86 processors that have aprotected mode,i.e. the 80286 and later processors, also have three descriptor registers (GDTR, LDTR,IDTR) and a task register (TR).

32-bit x86 processors (starting with the 80386) also include various special/miscellaneous registers such ascontrol registers(CR0 through 4, CR8 for 64-bit only),debug registers(DR0 through 3, plus 6 and 7),test registers(TR3 through 7; 80486 only), andmodel-specific registers(MSRs, appearing with the Pentium).

AVX-512has eight extra 64-bit mask registers K0–K7 for selecting elements in a vector register. Depending on the vector register and element widths, only a subset of bits of the mask register may be used by a given instruction.

Purpose

Although the main registers (with the exception of the instruction pointer) are "general-purpose" in the 32-bit and 64-bit versions of the instruction set and can be used for anything, it was originally envisioned that they be used for the following purposes:

• AL/AH/AX/EAX/RAX: Accumulator
• CL/CH/CX/ECX/RCX: Counter (for use with loops and strings)
• DL/DH/DX/EDX/RDX: Extend the precision of the accumulator (e.g. combine 32-bit EAX and EDX for 64-bit integer operations in 32-bit code)
• BL/BH/BX/EBX/RBX: Base index (for use with arrays)
• SP/ESP/RSP: Stack pointer for top address of the stack.
• BP/EBP/RBP: Stack base pointer for holding the address of the currentstack frame.
• SI/ESI/RSI:Source indexforstringoperations.
• DI/EDI/RDI:Destination indexfor string operations.
• IP/EIP/RIP: Instruction pointer. Holds theprogram counter,the address of next instruction.

Segment registers:

• CS: Code
• DS: Data
• SS: Stack
• ES: Extra data
• FS: Extra data #2
• GS: Extra data #3

No particular purposes were envisioned for the other 8 registers available only in 64-bit mode.

Some instructions compile and execute more efficiently when using these registers for their designed purpose. For example, using AL as anaccumulatorand adding an immediate byte value to it produces the efficientadd to ALopcodeof 04h, whilst using the BL register produces the generic and longeradd to registeropcode of 80C3h. Another example is double precision division and multiplication that works specifically with the AX and DX registers.

Modern compilers benefited from the introduction of thesibbyte (scale-index-base byte) that allows registers to be treated uniformly (minicomputer-like). However, using the sib byte universally is non-optimal, as it produces longer encodings than only using it selectively when necessary. (The main benefit of the sib byte is the orthogonality and more powerful addressing modes it provides, which make it possible to save instructions and the use of registers for address calculations such as scaling an index.) Some special instructions lost priority in the hardware design and became slower than equivalent small code sequences. A notable example is the LODSW instruction.

Structure

General Purpose Registers (A, B, C and D)

64	56	48	40	32	24	16	8
R?X
				E?X
						?X
						?H	?L

64-bit mode-only General Purpose Registers (R8, R9, R10, R11, R12, R13, R14, R15)

64	56	48	40	32	24	16	8
?
				?D
						?W
							?B

Segment Registers (C, D, S, E, F and G)

16	8
?S

Pointer Registers (S and B)

64	56	48	40	32	24	16	8
R?P
				E?P
						?P
							?PL

Note: The?PL registers are only available in 64-bit mode.

Index Registers (S and D)

64	56	48	40	32	24	16	8
R?I
				E?I
						?I
							?IL

Note: The?IL registers are only available in 64-bit mode.

Instruction Pointer Register (I)

64	56	48	40	32	24	16	8
RIP
				EIP
						IP

Operating modes

Real mode

Main article:Real mode

Real Address mode,commonly called Real mode, is an operating mode of8086and later x86-compatibleCPUs.Real mode is characterized by a 20-bit segmented memory address space (meaning that only slightly more than 1MiBof memory can be addressed), direct software access to peripheral hardware, and no concept ofmemory protectionormultitaskingat the hardware level. All x86 CPUs in the80286series and later start up in real mode at power-on;80186CPUs and earlier had only one operational mode, which is equivalent to real mode in later chips. (On the IBM PC platform, direct software access to the IBMBIOSroutines is available only in real mode, since BIOS is written for real mode. However, this is not a property of the x86 CPU but of the IBM BIOS design.)

In order to use more than 64 KB of memory, the segment registers must be used. This created great complications for compiler implementors who introduced odd pointer modes such as "near", "far" and "huge" to leverage the implicit nature of segmented architecture to different degrees, with some pointers containing 16-bit offsets within implied segments and other pointers containing segment addresses and offsets within segments. It is technically possible to use up to 256 KB of memory for code and data, with up to 64 KB for code, by setting all four segment registers once and then only using 16-bit offsets (optionally with default-segment override prefixes) to address memory, but this puts substantial restrictions on the way data can be addressed and memory operands can be combined, and it violates the architectural intent of the Intel designers, which is for separate data items (e.g. arrays, structures, code units) to be contained in separate segments and addressed by their own segment addresses, in new programs that are not ported from earlier 8-bit processors with 16-bit address spaces.

Unreal mode

Main article:Unreal mode

Unreal mode is used by some 16-bitoperating systemsand some 32-bitboot loaders.

System Management Mode

See also:System Management Mode

The System Management Mode (SMM) is only used by the system firmware (BIOS/UEFI), not byoperating systemsand applications software. The SMM code is running in SMRAM.

Protected mode

Main article:Protected mode

In addition to real mode, the Intel 80286 supports protected mode, expanding addressablephysical memoryto 16MBand addressablevirtual memoryto 1GB,and providingprotected memory,which prevents programs from corrupting one another. This is done by using the segment registers only for storing an index into a descriptor table that is stored in memory. There are two such tables, theGlobal Descriptor Table(GDT) and theLocal Descriptor Table(LDT), each holding up to 8192 segment descriptors, each segment giving access to 64 KB of memory. In the 80286, a segment descriptor provides a 24-bitbase address,and this base address is added to a 16-bit offset to create an absolute address. The base address from the table fulfills the same role that the literal value of the segment register fulfills in real mode; the segment registers have been converted from direct registers to indirect registers. Each segment can be assigned one of fourringlevels used for hardware-basedcomputer security.Each segment descriptor also contains a segment limit field which specifies the maximum offset that may be used with the segment. Because offsets are 16 bits, segments are still limited to 64 KB each in 80286 protected mode.

Each time a segment register is loaded in protected mode, the 80286 must read a 6-byte segment descriptor from memory into a set of hidden internal registers. Thus, loading segment registers is much slower in protected mode than in real mode, and changing segments very frequently is to be avoided. Actual memory operations using protected mode segments are not slowed much because the 80286 and later have hardware to check the offset against the segment limit in parallel with instruction execution.

TheIntel 80386extended offsets and also the segment limit field in each segment descriptor to 32 bits, enabling a segment to span the entire memory space. It also introduced support in protected mode forpaging,a mechanism making it possible to use pagedvirtual memory(with 4 KB page size). Paging allows the CPU to map any page of the virtual memory space to any page of the physical memory space. To do this, it uses additional mapping tables in memory called page tables. Protected mode on the 80386 can operate with paging either enabled or disabled; the segmentation mechanism is always active and generates virtual addresses that are then mapped by the paging mechanism if it is enabled. The segmentation mechanism can also be effectively disabled by setting all segments to have a base address of 0 and size limit equal to the whole address space; this also requires a minimally-sized segment descriptor table of only four descriptors (since the FS and GS segments need not be used).

Paging is used extensively by modern multitasking operating systems.Linux,386BSDandWindows NTwere developed for the 386 because it was the first Intel architecture CPU to support paging and 32-bit segment offsets. The 386 architecture became the basis of all further development in the x86 series.

x86 processors that support protected mode boot intoreal modefor backward compatibility with the older 8086 class of processors. Upon power-on (a.k.a.booting), the processor initializes in real mode, and then begins executing instructions. Operating system boot code, which might be stored inread-only memory,may place the processor into theprotected modeto enable paging and other features. Conversely, segment arithmetic, a common practice in real mode code, is not allowed in protected mode.

Virtual 8086 mode

Main article:Virtual 8086 mode

There is also a sub-mode of operation in 32-bit protected mode (a.k.a. 80386 protected mode) calledvirtual 8086 mode,also known asV86 mode.This is basically a special hybrid operating mode that allows real mode programs and operating systems to run while under the control of a protected mode supervisor operating system. This allows for a great deal of flexibility in running both protected mode programs and real mode programs simultaneously. This mode is exclusively available for the 32-bit version of protected mode; it does not exist in the 16-bit version of protected mode, or in long mode.

Long mode

Main article:Long mode

In the mid 1990s, it was obvious that the 32-bit address space of the x86 architecture was limiting its performance in applications requiring large data sets. A 32-bit address space would allow the processor to directly address only 4 GB of data, a size surpassed by applications such asvideo processinganddatabase engines.Using 64-bit addresses, it is possible to directly address 16EiBof data, although most 64-bit architectures do not support access to the full 64-bit address space; for example, AMD64 supports only 48 bits from a 64-bit address, split into four paging levels.

In 1999,AMDpublished a (nearly) complete specification for a64-bitextension of the x86 architecture which they calledx86-64with claimed intentions to produce. That design is currently used in almost all x86 processors, with some exceptions intended forembedded systems.

Mass-producedx86-64chips for the general market were available four years later, in 2003, after the time was spent for working prototypes to be tested and refined; about the same time, the initial namex86-64was changed toAMD64.The success of the AMD64 line of processors coupled with lukewarm reception of the IA-64 architecture forced Intel to release its own implementation of the AMD64 instruction set. Intel had previously implemented support for AMD64but opted not to enable it in hopes that AMD would not bring AMD64 to market before Itanium's new IA-64 instruction set was widely adopted. It branded its implementation of AMD64 asEM64T,and later rebranded itIntel 64.

In its literature and product version names, Microsoft and Sun refer to AMD64/Intel 64 collectively asx64in the Windows andSolarisoperating systems.Linux distributionsrefer to it either as "x86-64", its variant "x86_64", or "amd64".BSDsystems use "amd64" whilemacOSuses "x86_64".

Long mode is mostly an extension of the 32-bit instruction set, but unlike the 16–to–32-bit transition, many instructions were dropped in the 64-bit mode. This does not affect actual binary backward compatibility (which would execute legacy code in other modes that retain support for those instructions), but it changes the way assembler and compilers for new code have to work.

This was the first time that a major extension of the x86 architecture was initiated and originated by a manufacturer other than Intel. It was also the first time that Intel accepted technology of this nature from an outside source.

Extensions

Floating-point unit

Main article:x87

Further information:Floating-point unit

Early x86 processors could be extended withfloating-pointhardware in the form of a series of floating-pointnumericalco-processorswith names like8087,80287 and 80387, abbreviated x87. This was also known as the NPX (Numeric Processor eXtension), an apt name since the coprocessors, while used mainly for floating-point calculations, also performed integer operations on both binary and decimal formats. With very few exceptions, the 80486 and subsequent x86 processors then integrated this x87 functionality on chip which made the x87 instructions ade factointegral part of the x86 instruction set.

Each x87 register, known as ST(0) through ST(7), is 80 bits wide and stores numbers in theIEEE floating-point standarddouble extended precision format. These registers are organized as a stack with ST(0) as the top. This was done in order to conserve opcode space, and the registers are therefore randomly accessible only for either operand in a register-to-register instruction; ST0 must always be one of the two operands, either the source or the destination, regardless of whether the other operand is ST(x) or a memory operand. However, random access to the stack registers can be obtained through an instruction which exchanges any specified ST(x) with ST(0).

The operations include arithmetic and transcendental functions, including trigonometric and exponential functions, and instructions that load common constants (such as 0; 1; e, the base of the natural logarithm; log2(10); and log10(2)) into one of the stack registers. While the integer ability is often overlooked, the x87 can operate on larger integers with a single instruction than the 8086, 80286, 80386, or any x86 CPU without to 64-bit extensions can, and repeated integer calculations even on small values (e.g., 16-bit) can be accelerated by executing integer instructions on the x86 CPU and the x87 in parallel. (The x86 CPU keeps running while the x87 coprocessor calculates, and the x87 sets a signal to the x86 when it is finished or interrupts the x86 if it needs attention because of an error.)

MMX

Main article:MMX (instruction set)

MMX is aSIMDinstruction set designed by Intel and introduced in 1997 for thePentium MMXmicroprocessor.The MMX instruction set was developed from a similar concept first used on theIntel i860.It is supported on most subsequent IA-32 processors by Intel and other vendors. MMX is typically used for video processing (in multimedia applications, for instance).

MMX added 8 new registers to the architecture, known as MM0 through MM7 (henceforth referred to asMMn). In reality, these new registers were just aliases for the existing x87 FPU stack registers. Hence, anything that was done to the floating-point stack would also affect the MMX registers. Unlike the FP stack, these MMn registers were fixed, not relative, and therefore they were randomly accessible. The instruction set did not adopt the stack-like semantics so that existing operating systems could still correctly save and restore the register state when multitasking without modifications.

Each of the MMn registers are 64-bit integers. However, one of the main concepts of the MMX instruction set is the concept ofpacked data types,which means instead of using the whole register for a single 64-bit integer (quadword), one may use it to contain two 32-bit integers (doubleword), four 16-bit integers (word) or eight 8-bit integers (byte). Given that the MMX's 64-bit MMn registers are aliased to the FPU stack and each of the floating-point registers are 80 bits wide, the upper 16 bits of the floating-point registers are unused in MMX. These bits are set to all ones by any MMX instruction, which correspond to the floating-point representation ofNaNsor infinities.

3DNow!

Main article:3DNow!

In 1997, AMD introduced 3DNow!.The introduction of this technology coincided with the rise of3Dentertainment applications and was designed to improve the CPU'svector processingperformance of graphic-intensive applications. 3D video game developers and 3D graphics hardware vendors use 3DNow! to enhance their performance on AMD'sK6andAthlonseries of processors.

3DNow! was designed to be the natural evolution of MMX from integers to floating point. As such, it uses exactly the same register naming convention as MMX, that is MM0 through MM7.The only difference is that instead of packing integers into these registers, twosingle-precision floating-pointnumbers are packed into each register. The advantage of aliasing the FPU registers is that the same instruction and data structures used to save the state of the FPU registers can also be used to save 3DNow! register states. Thus no special modifications are required to be made to operating systems which would otherwise not know about them.

SSEand AVX

Main articles:Streaming SIMD Extensions,SSE2,SSE3,SSSE3,SSE4,andSSE5

In 1999, Intel introduced the Streaming SIMD Extensions (SSE)instruction set,following in 2000 with SSE2. The first addition allowed offloading of basic floating-point operations from the x87 stack and the second made MMX almost obsolete and allowed the instructions to be realistically targeted by conventional compilers. Introduced in 2004 along with thePrescottrevision of thePentium 4processor, SSE3 added specific memory andthread-handling instructions to boost the performance of Intel'sHyperThreadingtechnology. AMD licensed the SSE3 instruction set and implemented most of the SSE3 instructions for its revision E and later Athlon 64 processors. The Athlon 64 does not support HyperThreading and lacks those SSE3 instructions used only for HyperThreading.

SSE discarded all legacy connections to the FPU stack. This also meant that this instruction set discarded all legacy connections to previous generations of SIMD instruction sets like MMX. But it freed the designers up, allowing them to use larger registers, not limited by the size of the FPU registers. The designers created eight 128-bit registers, named XMM0 through XMM7. (InAMD64,the number of SSE XMM registers has been increased from 8 to 16.) However, the downside was that operating systems had to have an awareness of this new set of instructions in order to be able to save their register states. So Intel created a slightly modified version of Protected mode, called Enhanced mode which enables the usage of SSE instructions, whereas they stay disabled in regular Protected mode. An OS that is aware of SSE will activate Enhanced mode, whereas an unaware OS will only enter into traditional Protected mode.

SSE is a SIMD instruction set that works only on floating-point values, like 3DNow!. However, unlike 3DNow! it severs all legacy connection to the FPU stack. Because it has larger registers than 3DNow!, SSE can pack twice the number ofsingle precisionfloats into its registers. The original SSE was limited to only single-precision numbers, like 3DNow!. The SSE2 introduced the capability to packdouble precisionnumbers too, which 3DNow! had no possibility of doing since a double precision number is 64-bit in size which would be the full size of a single 3DNow! MMn register. At 128 bits, the SSE XMMn registers could pack two double precision floats into one register. Thus SSE2 is much more suitable for scientific calculations than either SSE1 or 3DNow!, which were limited to only single precision. SSE3 does not introduce any additional registers.

Main articles:Advanced Vector ExtensionsandAVX-512

The Advanced Vector Extensions (AVX) doubled the size of SSE registers to 256-bit YMM registers. It also introduced the VEX coding scheme to accommodate the larger registers, plus a few instructions to permute elements. AVX2 did not introduce extra registers, but was notable for the addition for masking,gather,and shuffle instructions.

AVX-512 features yet another expansion to 32 512-bit ZMM registers and a new EVEX scheme. Unlike its predecessors featuring a monolithic extension, it is divided into many subsets that specific models of CPUs can choose to implement.

Physical Address Extension (PAE)

Main article:Physical Address Extension

Physical Address Extensionor PAE was first added in the IntelPentium Pro,and later byAMDin the Athlon processors,to allow up to 64 GB of RAM to be addressed. Without PAE, physical RAM in 32-bit protected mode is usually limited to 4GB.PAE defines a different page table structure with wider page table entries and a third level of page table, allowing additional bits of physical address. Although the initial implementations on 32-bit processors theoretically supported up to 64 GB of RAM, chipset and other platform limitations often restricted what could actually be used.x86-64processors define page table structures that theoretically allow up to 52 bits of physical address, although again, chipset and other platform concerns (like the number of DIMM slots available, and the maximum RAM possible per DIMM) prevent such a large physical address space to be realized. On x86-64 processors PAE mode must be active before the switch tolong mode,and must remain active whilelong modeis active, so while in long mode there is no "non-PAE" mode. PAE mode does not affect the width of linear or virtual addresses.

x86-64

Main article:x86-64

Insupercomputerclusters(as tracked byTOP 500data and visualized on the diagram above, last updated 2013), the appearance of 64-bit extensions for the x86 architecture enabled 64-bit x86 processors by AMD and Intel (teal hatched and blue hatched, in the diagram, respectively) to replace most RISC processor architectures previously used in such systems (includingPA-RISC,SPARC,Alpha,and others), and 32-bit x86 (green on the diagram), even though Intel initially tried unsuccessfully to replace x86 with a new incompatible 64-bit architecture in theItaniumprocessor. The main non-x86 architecture which is still used, as of 2014, in supercomputing clusters is thePower ISAused byIBM Power microprocessors(blue with diamond tiling in the diagram), with SPARC as a distant second.

By the 2000s, 32-bit x86 processors' limits in memory addressing were an obstacle to their use in high-performance computing clusters and powerful desktop workstations. The aged 32-bit x86 was competing with much more advanced 64-bit RISC architectures which could address much more memory. Intel and the whole x86 ecosystem needed 64-bit memory addressing if x86 was to survive the 64-bit computing era, as workstation and desktop software applications were soon to start hitting the limits of 32-bit memory addressing. However, Intel felt that it was the right time to make a bold step and use the transition to 64-bit desktop computers for a transition away from the x86 architecture in general, an experiment which ultimately failed.

In 2001, Intel attempted to introduce a non-x86 64-bit architecture namedIA-64in itsItaniumprocessor, initially aiming for thehigh-performance computingmarket, hoping that it would eventually replace the 32-bit x86.While IA-64 was incompatible with x86, the Itanium processor did provideemulationabilities for translating x86 instructions into IA-64, but this affected the performance of x86 programs so badly that it was rarely, if ever, actually useful to the users: programmers should rewrite x86 programs for the IA-64 architecture or their performance on Itanium would be orders of magnitude worse than on a true x86 processor. The market rejected the Itanium processor since it brokebackward compatibilityand preferred to continue using x86 chips, and very few programs were rewritten for IA-64.

AMD decided to take another path toward 64-bit memory addressing, making sure backward compatibility would not suffer. In April 2003, AMD released the first x86 processor with 64-bit general-purpose registers, theOpteron,capable of addressing much more than 4GBof virtual memory using the newx86-64extension (also known as AMD64 or x64). The 64-bit extensions to the x86 architecture were enabled only in the newly introducedlong mode,therefore 32-bit and 16-bit applications and operating systems could simply continue using an AMD64 processor in protected or other modes, without even the slightest sacrifice of performanceand with full compatibility back to the original instructions of the 16-bit Intel 8086.The market responded positively, adopting the 64-bit AMD processors for both high-performance applications and business or home computers.

Seeing the market rejecting the incompatible Itanium processor and Microsoft supporting AMD64, Intel had to respond and introduced its own x86-64 processor, thePrescottPentium 4, in July 2004.As a result, the Itanium processor with its IA-64 instruction set is rarely used and x86, through its x86-64 incarnation, is still the dominant CPU architecture in non-embedded computers.

x86-64 also introduced theNX bit,which offers some protection against security bugs caused bybuffer overruns.

As a result of AMD's 64-bit contribution to the x86 lineage and its subsequent acceptance by Intel, the 64-bit RISC architectures ceased to be a threat to the x86 ecosystem and almost disappeared from the workstation market. x86-64 began to be utilized in powerfulsupercomputers(in itsAMD OpteronandIntel Xeonincarnations), a market which was previously the natural habitat for 64-bit RISC designs (such as theIBM Power microprocessorsorSPARCprocessors). The great leap toward 64-bit computing and the maintenance of backward compatibility with 32-bit and 16-bit software enabled the x86 architecture to become an extremely flexible platform today, with x86 chips being utilized from small low-power systems (for example,Intel QuarkandIntel Atom) to fast gaming desktop computers (for example,Intel Core i7andAMD FX/Ryzen), and even dominate large supercomputingclusters,effectively leaving only theARM32-bit and 64-bit RISC architecture as a competitor in thesmartphoneandtabletmarket.

Virtualization

Main article:x86 virtualization

Prior to 2005, x86 architecture processors were unable to meet thePopek and Goldberg requirements– a specification for virtualization created in 1974 byGerald J. PopekandRobert P. Goldberg.However, both proprietary and open-sourcex86 virtualizationhypervisor products were developed usingsoftware-based virtualization.Proprietary systems includeHyper-V,Parallels Workstation,VMware ESX,VMware Workstation,VMware Workstation PlayerandWindows Virtual PC,whilefree and open-sourcesystems includeQEMU,Kernel-based Virtual Machine,VirtualBox,andXen.

The introduction of the AMD-V and Intel VT-x instruction sets in 2005 allowed x86 processors to meet the Popek and Goldberg virtualization requirements.

AES

Main article:AES instruction set

APX (Advanced Performance Extensions)

APX (Advanced Performance Extensions) are extensions to double the number of general-purpose registers from 16 to 32 and add new features to improve general-purpose performance.These extensions have been called "generational"and "the biggest x86 addition since 64 bits".Intel contributed APX support toGNU Compiler Collection(GCC) 14.

According to the architecture specification,the main features of APX are:

• 16 additional general-purpose registers, called the Extended GPRs (EGPRs)
• Three-operand instruction formats for many integer instructions
• New conditional instructions for loads, stores, and comparisons with common instructions that do not modify flags
• Optimized register save/restore operations
• A 64-bit absolute direct jump instruction

Extended GPRs for general purpose instructions are encoded using 2-byteREX2prefix, while new instructions and extended operands for existingAVX/AVX2/AVX-512instructions are encoded withextended EVEXprefix which has four variants used for different groups of instructions.

See also

• x86 assembly language
• x86 calling conventions
• x86 instruction listings
• x86 memory segmentation
• CPUID
• Itanium
• x86-64
• 680x0,a competing architecture in the 16 & early 32bit eras
• PowerPC,a competing architecture in the later 32-bit and 64-bit eras
• Microarchitecture
• List of AMD processors
• List of Intel processors
• List of Intel CPU microarchitectures
• List of VIA microprocessor cores
• List of x86 manufacturers
• Interrupt request
• iAPX
• Speculative execution CPU vulnerabilities
• Tick–tock model
• Virtual legacy wires

Further reading

• Rosenblum, Mendel; Garfinkel, Tal (May 2005). "Virtual machine monitors: current technology and future trends".IEEE Computer.38(5): 39–47.CiteSeerX10.1.1.614.9870.doi:10.1109/MC.2005.176.S2CID10385623.

External links

• Why Intel can't seem to retire the x86
• 32/64-bit x86 Instruction Reference
• Intel Intrinsics Guide,an interactive reference tool for Intel intrinsic instructions
• Intel® 64 and IA-32 Architectures Software Developer's Manuals
• AMD Developer Guides, Manuals & ISA Documents, AMD64 Architecture