In thex86-64computer architecture,long modeis the mode where a64-bitoperating systemcan access 64-bitinstructionsandregisters.64-bit programs are run in a sub-mode called 64-bit mode, while32-bitprograms and16-bitprotected modeprograms are executed in a sub-mode called compatibility mode.Real modeorvirtual 8086 modeprograms cannot be natively run in long mode.

Overview

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An x86-64 processor acts identically to anIA-32processor when running in real mode or protected mode, which are supported modes when the processor isnotin long mode.

A bit in theCPUIDextended attributes field informs programs in real or protected modes if the processor can go to long mode, which allows a program to detect an x86-64 processor. This is similar to the CPUID attributes bit thatIntelIA-64processors use to allow programs to detect if they are running under IA-32 emulation.

With a computer running legacyBIOS,the BIOS and theboot loaderrun inreal mode.After execution passes to anoperating system kernelwhich supports x86-64, the kernel verifies CPU support for long mode and then executes the instructions to enter it. With a computer runningUEFI,the UEFI firmware (except CSM and legacyOption ROM), any UEFI boot loader, and the operating system kernel all run in Long mode.

Memory limitations

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While register sizes have increased to 64 bits from the previousx86 architecture,memory addressinghas not yet been increased to the full 64 bits. For the time being, it is impractical to equip computers with sufficient memory to require a full 64 bits. As long as that remains the case, load/store unit(s),cachetags,MMUsandTLBscan be simplified without any loss of usable memory. Despite this limitation, software is programmed using full 64-bitpointers,and will therefore be able to use progressively larger address spaces as they become supported by future processors and operating systems.

Current limits

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The first CPUs implementing the x86-64 architecture, namely the AMDAthlon 64/Opteron(K8) CPUs, had48-bitvirtual[1]: 129–130 and 40-bitphysical addressing.[1]: 4 

The virtual address space of these processors is divided into two 47-bit regions, one starting at the lowest possible address, the other extending down from the largest. Attempting to use addresses falling outside this range will cause ageneral protection fault.

The limit of physical addressing constrains how much installedRAMis able to be accessed by the computer. On accNUMAmultiprocessorsystem (Opteron) this includes the memory which is installed in the remote nodes, because the CPUs can directly address (and cache) all memory regardless if it is on the home node or remote. The 1TBlimit (40-bit) for physical memory for the K8 is huge by typical personal computer standards, but might have been a limitation for use in supercomputers. Consequently, theK10(or "10h" )microarchitectureimplements 48-bit physical addresses and so can address up to 256TBof RAM.[2]

When there is need, the microarchitecture can be expanded step by step without side-effects from software and simultaneously save cost with its implementation. For future expansion, the architecture supports expanding virtual address space to 64 bits, and physical memory addressing to 52 bits (limited by thepage tableentry format).[3]This would allow the processor to address 264bytes (16exabytes) of virtual address space and 252bytes (4petabytes) of physical address space.

See also

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References

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  1. ^ab"AMD64 Architecture Programmer's Manual Volume 2: System Programming"(PDF).2016.Retrieved2015-04-09.
  2. ^"BIOS and Kernel Developer's Guide (BKDG) For AMD Family 10h Processors"(PDF).p. 30.Retrieved2015-04-09.Physical address space increased to 48 bits.
  3. ^AMD 2016,p. 24: "The AMD64 architecture enhances this support to allow translation of 64-bit virtual addresses into 52-bit physical addresses, although processor implementations can support smaller virtual-address and physical-address spaces."
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