M·COREis a low-power,RISC-basedmicrocontrollerarchitecturedeveloped byMotorola(subsequentlyFreescale,now part ofNXP), intended for use inembedded systems.Introduced in late 1997, the architecture combines a32-bitinternal data path with16-bitinstructions,[1]and includes a four-stageinstruction pipeline.Initial implementations used a 360nm process and ran at 50 MHz.
M·CORE processors[2]employ avon Neumann architecturewith shared program and data bus—executing instructions from within data memory is possible. Motorola engineers designed M·CORE to havelow power consumptionand highcode density.[3]
References
edit- ^M-CORE, microRISC Engine, Programmers Reference Manual(PDF)(Revision 1.0 ed.), Motorola, Inc., 1997, archived fromthe original(PDF)on 2016-03-04
- ^MCore2114, 2113, 2112, Advanced Information
- ^ M•CORE Architectural Brief. 1997.
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