Wikipedia

MMX (instruction set)

This article is about the instruction set for Intel Pentium and Pentium II processors. For the operating system that used the abbreviation name as the latest version, seeWindows 3.0.

MMXis asingle instruction, multiple data(SIMD)instruction set architecturedesigned byIntel,introduced on January 8, 1997[1][2]with itsPentiumP5 (microarchitecture)based line ofmicroprocessors,named "Pentium with MMX Technology".[3]It developed out of a similar unit introduced on theIntel i860,[4]and earlier theIntel i750video pixel processor. MMX is aprocessor supplementary capabilitythat is supported onIA-32processors by Intel and other vendors as of 1997.AMD also added MMX instruction set in itsK6processor.

Pentium with MMX

The New York Timesdescribed the initial push, includingSuper Bowladvertisements, as focused on "a new generation of glitzy multimedia products, including videophones and 3-D video games."[5]

MMX has subsequently been extended by several programs by Intel and others:3DNow!,Streaming SIMD Extensions(SSE), and ongoing revisions ofAdvanced Vector Extensions(AVX).

Overview

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Naming

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MMX is officially a meaninglessinitialism[6]trademarkedby Intel;[7]unofficially, the initials have been variously explained as standing for

  • MultiMedia eXtension,[1]or
  • Matrix Math eXtension.[8]

Advanced Micro Devices(AMD), during one of its many court battles with Intel, produced marketing material from Intel indicating that MMX stood for "Matrix Math Extensions".[citation needed]Since aninitialismcannot be trademarked,[citation needed]this was an attempt to invalidate Intel's trademark. In 1995, Intel filed suit against AMD and Cyrix Corp. for misuse of its trademark MMX. AMD and Intel settled, with AMD acknowledging MMX as a trademark owned by Intel, and with Intel granting AMD rights to use the MMX trademark as a technology name, but not a processor name.[9]

Technical details

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Pentium II processor with MMX technology

MMX defines eightprocessor registers,named MM0 through MM7, and operations that operate on them. Each register is 64 bits wide and can be used to hold either 64-bitintegers,or multiple smaller integers in a "packed" format: one instruction can then be applied to two 32-bit integers, four 16-bit integers, or eight 8-bit integers at once.[10]

MMX provides only integer operations. When originally developed, for theIntel i860,the use of integer math made sense (both 2D and 3D calculations required it), but as graphics cards that did much of this became common, integerSIMDin the CPU became somewhat redundant for graphical applications.[citation needed]Alternatively, thesaturation arithmeticoperations in MMX could[vague]significantly speed up somedigital signal processingapplications.[citation needed]

To avoid compatibility problems with thecontext switchmechanisms in existing operating systems, the MMX registers are aliases for the existingx87floating-point unit(FPU) registers, which context switches would already save and restore. Unlike the x87 registers, which behave like astack,the MMX registers are each directly addressable (random access).

Any operation involving the floating-point stack might also affect the MMX registers and vice versa, so this aliasing makes it difficult to work with floating-point and SIMD operations in the same program.[11]To maximize performance, software often used the processor exclusively in one mode or the other, deferring the relatively slow switch between them as long as possible.

Each 64-bit MMX register corresponds to themantissapart of an 80-bit x87 register. The upper 16 bits of the x87 registers thus go unused in MMX, and these bits are all set to ones, making themNot a Number(NaN) data types, or infinities in the floating-point representation. This can be used by software to decide whether a given register's content is intended as floating-point or SIMD data.

Software support

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Software support for MMX developed slowly.[5]Intel's C Compilerand related development tools obtainedintrinsicsfor invoking MMX instructions and Intel releasedlibrariesof common vectorized algorithms using MMX. Both Intel andMetrowerksattemptedautomatic vectorizationin their compilers, but the operations in theCprogramming language mapped poorly onto the MMX instruction set and custom algorithms as of 2000 typically still had to be written inassembly language.[11]

Successors

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AMD, a competingx86microprocessor vendor, enhanced Intel's MMX with their own3DNow!instruction set. 3DNow is best known for adding single-precision (32-bit) floating-point support to the SIMD instruction-set, among other integer and more general enhancements.

Following MMX, Intel's next major x86 extension was theStreaming SIMD Extensions(SSE), introduced with thePentium IIIfamily[12]in 1999,[13]roughly a year after AMD's 3DNow! was introduced.

SSE addressed the core shortcomings of MMX (inability to mix integer-SIMD ops with any floating-point ops) by creating a new 128-bit wide register file (XMM0–XMM7) and new SIMD instructions for it. Like 3DNow!, SSE focused exclusively on single-precision floating-point operations (32-bit); integer SIMD operations were still performed using the MMX register and instruction set. However, the new XMM register-file allowed SSE SIMD-operations to be freely mixed with either MMX or x87 FPU ops.

Streaming SIMD Extensions 2(SSE2), introduced with thePentium 4,further extended the x86 SIMD instruction set with integer (8/16/32 bit) and double-precision floating-point data support for the XMM register file. SSE2 also allowed the MMXoperation codes(opcodes) to use XMM register operands, extended to even wider YMM and ZMM registers by later SSE revisions.

MMX in embedded applications

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Intel's andMarvell Technology Group'sXScalemicroprocessor core starting with PXA270 include anSIMDinstruction set architectureextension to theARM architecturecore namedIntel Wireless MMX Technology(iwMMXt) which functions are similar to those of theIA-32MMX extension.[14][15][16]It provides arithmetic and logic operations on 64-bit integer numbers, in which the software may choose to instead perform two 32-bit, four 16-bit or eight 8-bit operations in one instruction. The extension contains 16 data registers of 64-bits and eight control registers of 32-bits. All registers are accessed through standard ARM architecture coprocessor mapping mechanism. iwMMXt occupies coprocessors 0 and 1 space, and some of its opcodes clash with the opcodes of the earlier floating-point extension, FPA.[citation needed]

Later versions of Marvell's ARM processors support bothWireless MMX(WMMX) andWireless MMX2(WMMX2) opcodes.

See also

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References

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  1. ^ab"Makers Unveil PCs With Intel's MMX Chip".The New York Times.January 9, 1997.Archivedfrom the original on January 13, 2019.RetrievedJanuary 13,2019.Intel's new multimedia extension technology, called MMX,...
  2. ^Ch, Rajiv; rasekaran (January 8, 1997)."Intel to unveil faster Pentium chip".The Washington Post.Archivedfrom the original on January 14, 2019.RetrievedJanuary 13,2019.
  3. ^"Embedded Pentium Processors with MMX Technology".Intel.Archivedfrom the original on August 11, 2010.RetrievedJuly 28,2007.
  4. ^Mittal, Millind; Peleg, Alex; Weiser, Uri (1997)."MMX Technology Architecture Overview"(PDF).Intel Technology Journal.1(3).Archived(PDF)from the original on March 4, 2016.RetrievedOctober 29,2015.
  5. ^abCalem, Robert E. (January 24, 1997)."Intel's MMX: The Technology Behind the Hoopla".The New York Times.Archivedfrom the original on January 13, 2019.RetrievedJanuary 13,2019.
  6. ^Tanaka, Jennifer (February 16, 1997)."A new chip off the block".Newsweek.Archivedfrom the original on August 31, 2019.RetrievedAugust 31,2019.the name, which doesn't stand for anything
  7. ^"Intel | Data Center Solutions, IoT, and PC Innovation".Archivedfrom the original on December 17, 2013.RetrievedDecember 17,2013.
  8. ^Zhang, Peng (January 1, 2010)."CHAPTER 5 - Microprocessors".Advanced Industrial Control Technology.(12) MMX technology: William Andrew Publishing. pp. 155–214.ISBN978-1-4377-7807-6.RetrievedJune 2,2024.{{cite book}}:CS1 maint: location (link)
  9. ^"Intel and Advance Micro agree on chip trademark".The New York Times.April 22, 1997.Archivedfrom the original on January 13, 2019.RetrievedJanuary 13,2019.
  10. ^Pfeiffer, Joseph J. Jr. (1997)."MMX Microarchitecture of Pentium Processors With MMX Technology and Pentium II Microprocessors"(PDF).Intel Technology Journal.Archived fromthe original(PDF)on January 12, 2011.RetrievedSeptember 1,2017.
  11. ^abConte, G.; Tommesani, S.; Zanichelli, F. (2000).The long and winding road to high-performance image processing with MMX/SSE(PDF).Proceedings of IEEE International Workshop on Computer Architectures for Machine Perception. Archived fromthe original(PDF)on January 28, 2016.
  12. ^Kay, Alan S. (February 26, 1999)."Pentium III: Buy the Numbers?".The Washington Post.Archivedfrom the original on April 15, 2019.RetrievedJanuary 13,2019.
  13. ^"Microprocessor Hall of Fame".Intel Museum.Archived fromthe originalon April 6, 2008.
  14. ^"Intel Brings MMX™ Technology To Intel® Personal Internet Client Architecture-Based Wireless Devices".RetrievedJuly 28,2022.
  15. ^"Intel Delivers Next-Generation Processors Specifically Designed For Cell Phones And Wireless PDAs".Archivedfrom the original on January 2, 2012.RetrievedJuly 28,2022.
  16. ^"World's smallest PXA270 embedded CPU card?".EE Times.September 15, 2004.RetrievedJuly 28,2022.
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