Memory-mapped I/O and port-mapped I/O

For more generic meanings of input/output ports, seeComputer port (hardware).For memory-mapped file I/O, seeMemory-mapped file.

"Port-mapped I/O" redirects here. For the related concept in computing, seeProgrammed input–output.

"MMIO" redirects here. For the airport in Mexico with the code MMIO, seeSaltillo Airport.

Memory-mapped I/O(MMIO) andport-mapped I/O(PMIO) are two complementary methods of performinginput/output(I/O) between thecentral processing unit(CPU) andperipheral devicesin acomputer(often mediating access viachipset). An alternative approach is using dedicated I/O processors, commonly known aschannelsonmainframe computers,which execute their owninstructions.

Memory-mapped I/Ouses the sameaddress spaceto address bothmain memoryandI/O devices.The memory andregistersof the I/O devices are mapped to (associated with) address values, so a memory address may refer to either a portion ofphysical RAMor to memory and registers of the I/O device. Thus, the CPU instructions used to access the memory (e.g.MOV...) can also be used for accessing devices. Each I/O device either monitors the CPU's address bus and responds to any CPU access of an address assigned to that device, connecting thesystem busto the desired device'shardware register,or uses a dedicated bus.

To accommodate the I/O devices, some areas of the address bus used by the CPU must be reserved for I/O and must not be available for normal physical memory; the range of addresses used for I/O devices is determined by the hardware. The reservation may be permanent, or temporary (as achieved viabank switching). An example of the latter is found in theCommodore 64,which uses a form of memory mapping to causeRAMor I/O hardware to appear in the0xD000–0xDFFFrange.

Port-mapped I/Ooften uses a special class of CPU instructions designed specifically for performing I/O, such as theinandoutinstructions found on microprocessors based on thex86architecture. Different forms of these two instructions can copy one, two or four bytes (outb,outwandoutl,respectively) between theEAX registeror one of that register's subdivisions on the CPU and a specified I/O port address which is assigned to an I/O device. I/O devices have a separate address space from general memory, either accomplished by an extra "I/O" pin on the CPU's physical interface, or an entirebusdedicated to I/O. Because the address space for I/O is isolated from that for main memory, this is sometimes referred to as isolated I/O.On the x86 architecture, index/data pair is often used for port-mapped I/O.

Overview

Different CPU-to-device communication methods, such as memory mapping, do not affect thedirect memory access(DMA) for a device, because, by definition, DMA is a memory-to-device communication method that bypasses the CPU.

Hardwareinterruptsare another communication method between the CPU and peripheral devices, however, for a number of reasons, interrupts are always treated separately. An interrupt is device-initiated, as opposed to the methods mentioned above, which are CPU-initiated. It is also unidirectional, as information flows only from device to CPU. Lastly, each interrupt line carries only onebitof information with a fixed meaning, namely "an event that requires attention has occurred in a device on this interrupt line".

I/O operations can slow memory access if the address and data buses are shared. This is because the peripheral device is usually much slower than main memory. In some architectures, port-mapped I/O operates via a dedicated I/O bus, alleviating the problem.

One merit of memory-mapped I/O is that, by discarding the extra complexity that port I/O brings, a CPU requires less internal logic and is thus cheaper, faster, easier to build, consumes less power and can be physically smaller; this follows the basic tenets ofreduced instruction set computing,and is also advantageous inembedded systems.The other advantage is that, because regular memory instructions are used to address devices, all of the CPU's addressing modes are available for the I/O as well as the memory, and instructions that perform anALUoperation directly on a memory operand (loading an operand from a memory location, storing the result to a memory location, or both) can be used with I/O device registers as well. In contrast, port-mapped I/O instructions are often very limited, often providing only for simple load-and-store operations between CPU registers and I/O ports, so that, for example, to add a constant to a port-mapped device register would require three instructions: read the port to a CPU register, add the constant to the CPU register, and write the result back to the port.

As16-bitprocessors have become obsolete and replaced with32-bitand64-bitin general use, reserving ranges of memory address space for I/O is less of a problem, as the memory address space of the processor is usually much larger than the required space for all memory and I/O devices in a system. Therefore, it has become more frequently practical to take advantage of the benefits of memory-mapped I/O. However, even with address space being no longer a major concern, neither I/O mapping method is universally superior to the other, and there will be cases where using port-mapped I/O is still preferable.

x86

Memory-mapped I/O is preferred inIA-32andx86-64based architectures because the instructions that perform port-based I/O are limited to one register: EAX, AX, and AL are the only registers that data can be moved into or out of, and either a byte-sized immediate value in the instruction or a value in register DX determines which port is the source or destination port of the transfer.Since any general-purpose register can send or receive data to or from memory and memory-mapped I/O devices, memory-mapped I/O uses fewer instructions and can run faster than port I/O.AMDdid not extend the port I/O instructions when defining thex86-64architecture to support 64-bit ports, so 64-bit transfers cannot be performed using port I/O.

On newer Intel platforms beginning with 20085 series,I/O devices on the chipset directly communicate via a dedicatedDirect Media Interface(DMI) bus.

Memory barriers

Since thecachesmediate accesses to memory addresses, data written to different addresses may reach the peripherals' memory or registers out of the program order, i.e. if software writes data to an address and then writes data to another address, the cachewrite bufferdoes not guarantee that the data will reach the peripherals in that order.Any program that does not includecache-flushinginstructions after each write in the sequence may see unintended IO effects if a cache system optimizes the write order. Writes to memory can often be reordered to reduce redundancy or to make better use of memory access cycles without changing the final state of what got stored; whereas, the same optimizations might completely change the meaning and effect of writes to memory-mapped I/O regions.

Lack of foresight in the choice of memory-mapped I/O regions led to many of the RAM-capacity barriers in older generations of computers. Designers rarely expected machines to grow to make full use of an architecture's theoretical RAM capacity, and thus often used some of the high-order bits of the address-space as selectors for memory-mapped I/O functions. For example, the640 KB barrierin the IBM PC and derivatives is due to reserving the region between 640 and 1024 KB (64k segments 10 through 16) for theUpper Memory Area.This choice initially made little impact, but it eventually limited the total amount of RAM available within the 20-bit available address space. The3 GB barrierandPCI holeare similar manifestations of this with 32-bit address spaces, exacerbated by details of thex86boot process andMMUdesign. 64-bit architectures often technically have similar issues, but these only rarely have practical consequences.

Examples

A sample system memory map

Address range (hexadecimal)	Size	Device
0000–7FFF	32 KiB	RAM
8000–80FF	256 bytes	General-purpose I/O
9000–90FF	256 bytes	Sound controller
A000–A7FF	2 KiB	Video controller/text-mapped display RAM
C000–FFFF	16 KiB	ROM

A simple system built around an8-bitmicroprocessormight provide 16-bit address lines, allowing it to address up to 64kibibytes(KiB) of memory. On such a system, the first 32 KiB of address space may be allotted torandom access memory(RAM), another 16 KiB toread-only memory(ROM) and the remainder to a variety of other devices such as timers, counters, video display chips, sound generating devices, etc.

The hardware of the system is arranged so that devices on the address bus will only respond to particular addresses which are intended for them, while all other addresses are ignored. This is the job of theaddress decoding circuitry,and that establishes thememory mapof the system. As a result, system's memory map may look like in the table on the right. This memory map contains gaps, which is also quite common in actual system architectures.

Assuming the fourth register of the video controller sets the background colour of the screen, the CPU can set this colour by writing a value to the memory location A003 using its standard memory write instruction. Using the same method, graphs can be displayed on a screen by writing character values into a special area of RAM within the video controller. Prior to cheapRAMthat enabledbit-mapped displays,this character cell method was a popular technique for computer video displays (seeText user interface).

Basic types of address decoding

Address decoding types, in which a device may decode addresses completely or incompletely, include the following:

Complete (exhaustive) decoding

1:1 mapping of unique addresses to one hardware register (physical memory location). Involves checking every line of theaddress bus.

Incomplete (partial) decoding

n:1 mapping of n unique addresses to one hardware register. Partial decoding allows a memory location to have more than one address, allowing the programmer to reference a memory location using n different addresses. It may also be done to simplify the decoding hardware by using simpler and often cheaper logic that examines only some address lines, when not all of the CPU's address space is needed. Commonly, the decoding itself is programmable, so the system can reconfigure its own memory map as required, though this is a newer development and generally in conflict with the intent of being cheaper.

Synonyms: foldback, multiply mapped, partially mapped, addressaliasing.

Linear decoding

Address lines are used directly without any decoding logic. This is done with devices such as RAMs and ROMs that have a sequence of address inputs, and with peripheral chips that have a similar sequence of inputs for addressing a bank of registers. Linear addressing is rarely used alone (only when there are few devices on the bus, as using purely linear addressing for more than one device usually wastes a lot of address space) but instead is combined with one of the other methods to select a device or group of devices within which the linear addressing selects a single register or memory location.

Port I/O via device drivers

In Windows-based computers, memory can also be accessed via specific drivers such as DOLLx8KD which gives I/O access in 8-, 16- and 32-bit on most Windows platforms starting from Windows 95 up to Windows 7. Installing I/O port drivers will ensure memory access by activating the drivers with simple DLL calls allowing port I/O and when not needed, the driver can be closed to prevent unauthorized access to the I/O ports.

Linux provides thepcimemutility to allow reading from and writing to MMIO addresses. The Linux kernel also allows tracing MMIO access from kernel modules (drivers) using the kernel'smmiotracedebug facility. To enable this, the Linux kernel should be compiled with the corresponding option enabled.mmiotraceis used for debugging closed-source device drivers.

See also

• Programmed input–output
• mmap,not to be confused with memory-mapped I/O
• Memory-mapped file
• Early examples of computers with port-mapped I/O
  • PDP-8
  • Nova
• PDP-11,an early example of a computer architecture using memory-mapped I/O
  • Unibus,a memory and I/O bus used by the PDP-11
• Bank switching
• Ralf Brown's Interrupt List
• Coprocessor
• Direct memory access
• Advanced Configuration and Power Interface(ACPI)
• Speculative execution CPU vulnerabilities