x86-64

"Intel 64" redirects here. For the Intel 64-bit architecture in Itanium chips, seeIA-64.

"x64" redirects here. For the New York City bus route, seeX64 (New York City bus).

x86-64(also known asx64,x86_64,AMD64,andIntel 64)is a64-bitversion of thex86instruction set,first announced in 1999. It introduced two new modes of operation, 64-bit mode and compatibility mode, along with a new 4-levelpagingmode.

AMDOpteron,the first CPU to introduce the x86-64 extensions in April 2003

The five-volume set of thex86-64 Architecture Programmer's Manual,as published and distributed by AMD in 2002

With 64-bit mode and the new paging mode, it supports vastly larger amounts ofvirtual memoryandphysical memorythan was possible on its32-bitpredecessors, allowing programs to store larger amounts of data in memory. x86-64 also expandsgeneral-purpose registersto 64-bit, and expands the number of them from 8 (some of which had limited or fixed functionality, e.g. for stack management) to 16 (fully general), and provides numerous other enhancements.Floating-point arithmeticis supported via mandatorySSE2-like instructions,andx87/MMXstyle registers are generally not used (but still available even in 64-bit mode); instead, a set of 16vector registers,128 bits each, is used. (Each register can store one or twodouble-precisionnumbers or one to foursingle-precisionnumbers, or various integer formats.) In 64-bit mode, instructions are modified to support 64-bitoperandsand 64-bitaddressing mode.

The compatibility mode defined in the architecture allows 16-bit and 32-bituser applicationsto run unmodified, coexisting with 64-bit applications if the 64-bit operating system supports them.As the full x86 16-bit and 32-bit instruction sets remain implemented in hardware without any intervening emulation, these olderexecutablescan run with little or no performance penalty,while newer or modified applications can take advantage of new features of the processor design to achieve performance improvements. Also, a processor supporting x86-64 still powers on inreal modefor fullbackward compatibilitywith the8086,as x86 processors supportingprotected modehave done since the80286.

The original specification, created byAMDand released in 2000, has been implemented by AMD,Intel,andVIA.TheAMD K8microarchitecture,in theOpteronandAthlon 64processors, was the first to implement it. This was the first significant addition to thex86architecture designed by a company other than Intel. Intel was forced to follow suit and introduced a modifiedNetBurstfamily which was software-compatible with AMD's specification.VIA Technologiesintroduced x86-64 in their VIA Isaiah architecture, with theVIA Nano.

The x86-64 architecture was quickly adopted for desktop and laptop personal computers and servers which were commonly configured for 16 GiB (gibibytes) of memory or more. It has effectively replaced the discontinued IntelItaniumarchitecture (formerlyIA-64), which was originally intended to replace the x86 architecture. x86-64 and Itanium are not compatible on the native instruction set level, and operating systems and applications compiled for one architecture cannot be run on the other natively.

AMD64

AMD64 logo

History

AMD64 (also variously referred to byAMDin their literature and documentation as “AMD 64-bit Technology” and “AMD x86-64 Architecture” ) was created as an alternative to the radically differentIA-64architecture designed byIntelandHewlett-Packard,which wasbackward-incompatiblewithIA-32,the 32-bit version of thex86architecture. AMD originally announced AMD64 in 1999with a full specification available in August 2000.As AMD was never invited to be a contributing party for the IA-64 architecture and any kind of licensing seemed unlikely, the AMD64 architecture was positioned by AMD from the beginning as an evolutionary way to add64-bit computingcapabilities to the existing x86 architecture while supporting legacy 32-bit x86code,as opposed to Intel's approach of creating an entirely new, completely x86-incompatible 64-bit architecture with IA-64.

The first AMD64-based processor, theOpteron,was released in April 2003.

Implementations

AMD's processors implementing the AMD64 architecture includeOpteron,Athlon 64,Athlon 64 X2,Athlon 64 FX,Athlon II(followed by "X2", "X3", or "X4" to indicate the number of cores, and XLT models),Turion 64,Turion 64 X2,Sempron( "Palermo" E6 stepping and all "Manila" models),Phenom(followed by "X3" or "X4" to indicate the number of cores),Phenom II(followed by "X2", "X3", "X4" or "X6" to indicate the number of cores),FX,Fusion/APUandRyzen/Epyc.

Architectural features

The primary defining characteristic of AMD64 is the availability of 64-bit general-purposeprocessor registers(for example,rax), 64-bitintegerarithmetic and logical operations, and 64-bitvirtual addresses.The designers took the opportunity to make other improvements as well.

Notable changes in the 64-bit extensions include:

64-bit integer capability

Allgeneral-purpose registers(GPRs) are expanded from 32bitsto 64 bits, and all arithmetic and logical operations, memory-to-register and register-to-memory operations, etc., can operate directly on 64-bit integers.Pushes and popson thestackdefault to 8-byte strides, andpointersare 8 bytes wide.

Additional registers

In addition to increasing the size of the general-purpose registers, the number of named general-purpose registers is increased from eight (i.e.eax,ecx,edx,ebx,esp,ebp,esi,edi) in x86 to 16 (i.e.rax,rcx,rdx,rbx,rsp,rbp,rsi,rdi,r8,r9,r10,r11,r12,r13,r14,r15). It is therefore possible to keep more local variables in registers rather than on the stack, and to let registers hold frequently accessed constants; arguments for small and fast subroutines may also be passed in registers to a greater extent.

AMD64 still has fewer registers than manyRISCinstruction sets(e.g.Power ISAhas 32 GPRs;64-bit ARM,RISC-VI,SPARC,Alpha,MIPS,andPA-RISChave 31) orVLIW-like machines such as theIA-64(which has 128 registers). However, an AMD64 implementation may have far more internal registers than the number of architectural registers exposed by the instruction set (seeregister renaming). (For example, AMD Zen cores have 168 64-bit integer and 160 128-bit vector floating-point physical internal registers.)

Additional XMM (SSE) registers

Similarly, the number of 128-bit XMM registers (used forStreaming SIMDinstructions) is also increased from 8 to 16.

The traditional x87 FPU register stack is not included in the register file size extension in 64-bit mode, compared with the XMM registers used by SSE2, which did get extended. Thex87register stack is not a simple register file although it does allow direct access to individual registers by low cost exchange operations.

Larger virtual address space

The AMD64 architecture defines a 64-bit virtual address format, of which the low-order 48 bits are used in current implementations.This allows up to 256TiB(2⁴⁸bytes) of virtual address space. The architecture definition allows this limit to be raised in future implementations to the full 64 bits,extending the virtual address space to 16EiB(2⁶⁴bytes).This is compared to just 4GiB(2³²bytes) for the x86.

This means that very large files can be operated on bymappingthe entire file into the process's address space (which is often much faster than working with file read/write calls), rather than having to map regions of the file into and out of the address space.

Larger physical address space

The original implementation of the AMD64 architecture implemented 40-bitphysical addressesand so could address up to 1 TiB (2⁴⁰bytes) of RAM.Current implementations of the AMD64 architecture (starting fromAMD 10h microarchitecture) extend this to 48-bit physical addressesand therefore can address up to 256 TiB (2⁴⁸bytes) of RAM. The architecture permits extending this to 52 bits in the future(limited by the page table entry format);this would allow addressing of up to 4 PiB of RAM. For comparison, 32-bit x86 processors are limited to 64 GiB of RAM inPhysical Address Extension(PAE) mode,or 4 GiB of RAM without PAE mode.

Larger physical address space in legacy mode

When operating inlegacy modethe AMD64 architecture supportsPhysical Address Extension(PAE) mode, as do most current x86 processors, but AMD64 extends PAE from 36 bits to an architectural limit of 52 bits of physical address. Any implementation, therefore, allows the same physical address limit as underlong mode.

Instruction pointer relative data access

Instructions can now reference data relative to the instruction pointer (RIP register). This makesposition-independent code,as is often used inshared librariesand code loaded at run time, more efficient.

SSE instructions

The original AMD64 architecture adopted Intel'sSSEandSSE2as core instructions. These instruction sets provide a vector supplement to the scalarx87FPU, for the single-precision and double-precision data types. SSE2 also offers integer vector operations, for data types ranging from 8bit to 64bit precision. This makes the vector capabilities of the architecture on par with those of the most advanced x86 processors of its time. These instructions can also be used in 32-bit mode. The proliferation of 64-bit processors has made these vector capabilities ubiquitous in home computers, allowing the improvement of the standards of 32-bit applications. The 32-bit edition of Windows 8, for example, requires the presence of SSE2 instructions.SSE3instructions and laterStreaming SIMD Extensionsinstruction sets are not standard features of the architecture.

No-Execute bit

The No-Execute bit orNX bit(bit 63 of the page table entry) allows the operating system to specify which pages of virtual address space can contain executable code and which cannot. An attempt to execute code from a page tagged "no execute" will result in a memory access violation, similar to an attempt to write to a read-only page. This should make it more difficult for malicious code to take control of the system via "buffer overrun"or" unchecked buffer "attacks. A similar feature has been available on x86 processors since the80286as an attribute ofsegment descriptors;however, this works only on an entire segment at a time.

Segmented addressinghas long been considered an obsolete mode of operation, and all current PC operating systems in effect bypass it, setting all segments to a base address of zero and (in their 32-bit implementation) a size of 4 GiB. AMD was the first x86-family vendor to implement no-execute in linear addressing mode. The feature is also available in legacy mode on AMD64 processors, and recent Intel x86 processors, when PAE is used.

Removal of older features

A few "system programming" features of the x86 architecture were either unused or underused in modern operating systems and are either not available on AMD64 in long (64-bit and compatibility) mode, or exist only in limited form. These include segmented addressing (although the FS and GS segments are retained in vestigial form for use as extra-base pointers to operating system structures),thetask state switchmechanism, andvirtual 8086 mode.These features remain fully implemented in "legacy mode", allowing these processors to run 32-bit and 16-bit operating systems without modifications. Some instructions that proved to be rarely useful are not supported in 64-bit mode, including saving/restoring of segment registers on the stack, saving/restoring of all registers (PUSHA/POPA), decimal arithmetic, BOUND and INTO instructions, and "far" jumps and calls with immediate operands.

Virtual address space details

Canonical form addresses

Canonical address space implementations (diagrams not to scale)

Current 48-bit implementation

57-bit implementation

64-bit implementation

Although virtual addresses are 64 bits wide in 64-bit mode, current implementations (and all chips that are known to be in the planning stages) do not allow the entire virtual address space of 2⁶⁴bytes (16EiB) to be used. This would be approximately four billion times the size of the virtual address space on 32-bit machines. Most operating systems and applications will not need such a large address space for the foreseeable future, so implementing such wide virtual addresses would simply increase the complexity and cost of address translation with no real benefit. AMD, therefore, decided that, in the first implementations of the architecture, only the least significant 48 bits of a virtual address would actually be used in address translation (page tablelookup).

In addition, the AMD specification requires that the most significant 16 bits of any virtual address, bits 48 through 63, must be copies of bit 47 (in a manner akin tosign extension). If this requirement is not met, the processor will raise an exception.Addresses complying with this rule are referred to as "canonical form."Canonical form addresses run from 0 through 00007FFF'FFFFFFFF, and from FFFF8000'00000000 through FFFFFFFF'FFFFFFFF, for a total of 256TiBof usable virtual address space. This is still 65,536 times larger than the virtual 4 GiB address space of 32-bit machines.

This feature eases later scalability to true 64-bit addressing. Many operating systems (including, but not limited to, theWindows NTfamily) take the higher-addressed half of the address space (namedkernel space) for themselves and leave the lower-addressed half (user space) for application code, user mode stacks, heaps, and other data regions.The "canonical address" design ensures that every AMD64 compliant implementation has, in effect, two memory halves: the lower half starts at 00000000'00000000 and "grows upwards" as more virtual address bits become available, while the higher half is "docked" to the top of the address space and grows downwards. Also, enforcing the "canonical form" of addresses by checking the unused address bits prevents their use by the operating system intagged pointersas flags, privilege markers, etc., as such use could become problematic when the architecture is extended to implement more virtual address bits.

The first versions of Windows for x64 did not even use the full 256 TiB; they were restricted to just 8 TiB of user space and 8 TiB of kernel space.Windows did not support the entire 48-bit address space untilWindows 8.1,which was released in October 2013.

Page table structure

The 64-bit addressing mode ( "long mode") is a superset ofPhysical Address Extensions(PAE); because of this,pagesizes may be 4KiB(2¹²bytes) or 2MiB(2²¹bytes).Long mode also supports page sizes of 1GiB(2³⁰bytes).Rather than the three-levelpage tablesystem used by systems in PAE mode, systems running inlong modeuse four levels of page table: PAE'sPage-Directory Pointer Tableis extended from four entries to 512, and an additionalPage-Map Level 4 (PML4) Tableis added, containing 512 entries in 48-bit implementations.A full mapping hierarchy of 4 KiB pages for the whole 48-bit space would take a bit more than 512GiBof memory (about 0.195% of the 256 TiB virtual space).

64 bit page table entry

Bits:	63	62… 52											51… 32
Content:	NX	reserved											Bit 51…32 of base address
Bits:	31… 12																				11… 9			8	7	6	5	4	3	2	1	0
Content:	Bit 31…12 of base address																				ign.			G	PAT	D	A	PCD	PWT	U/S	R/W	P

Intel has implemented a scheme with a5-level page table,which allows Intel 64 processors to support a 57-bit virtual address space.Further extensions may allow full 64-bit virtual address space and physical memory with 12-bit page table descriptors and 16- or 21-bit memory offsets for 64 KiB and 2 MiB page allocation sizes; the page table entry would be expanded to 128 bits to support additional hardware flags for page size and virtual address space size.

Operating system limits

The operating system can also limit the virtual address space. Details, where applicable, are given in the "Operating system compatibility and characteristics"section.

Physical address space details

Current AMD64 processors support a physical address space of up to 2⁴⁸bytes of RAM, or 256TiB.However, as of 2020,there were no known x86-64motherboardsthat support 256 TiB of RAM.The operating system may place additional limits on the amount of RAM that is usable or supported. Details on this point are given in the "Operating system compatibility and characteristics"section of this article.

Operating modes

The architecture has two primary modes of operation: long mode and legacy mode.

Operating		Operating systemrequired	Type of code being run	Size (in bits)		No. ofgeneral-purpose registers
mode	sub-mode			addresses	operands (default in italics)
Long mode	64-bit mode	64-bit OS, 64-bitUEFIfirmware, or the previous two interacting via a 64-bit firmware's UEFI interface	64-bit	64	8, 16,32,64	16
	Compatibility mode	Bootloaderor 64-bit OS	32-bit	32	8, 16,32	8
			16-bit protected mode	16	8,16,32	8
Legacy mode	Protected mode	Bootloader,32-bit OS, 32-bit UEFI firmware, or the latter two interacting via the firmware's UEFI interface	32-bit	32	8, 16,32	8
		16-bit protected mode OS	16-bit protected mode	16	8,16,32	8
	Virtual 8086 mode	16-bit protected mode or 32-bit OS	subset ofreal mode	16	8,16,32	8
	Unreal mode	Bootloaderor real mode OS	real mode	16, 20, 32	8,16,32	8
	Real mode	Bootloader,real mode OS, or any OS interfacing with a firmware'sBIOSinterface	real mode	16, 20,21	8,16,32	8

State diagram of the x86-64 operating modes

Long mode

Main article:Long mode

Long mode is the architecture's intended primary mode of operation; it is a combination of the processor's native 64-bit mode and a combined 32-bit and 16-bit compatibility mode. It is used by 64-bit operating systems. Under a 64-bit operating system, 64-bit programs run under 64-bit mode, and 32-bit and 16-bit protected mode applications (that do not need to use either real mode or virtual 8086 mode in order to execute at any time) run under compatibility mode. Real-mode programs and programs that use virtual 8086 mode at any time cannot be run in long mode unless those modes are emulated in software.However, such programs may be started from an operating system running in long mode on processors supportingVT-xorAMD-Vby creating a virtual processor running in the desired mode.

Since the basicinstruction setis the same, there is almost no performance penalty for executing protected mode x86 code. This is unlike Intel'sIA-64,where differences in the underlying instruction set mean that running 32-bit code must be done either in emulation of x86 (making the process slower) or with a dedicated x86 coprocessor. However, on the x86-64 platform, many x86 applications could benefit from a 64-bitrecompile,due to the additional registers in 64-bit code and guaranteed SSE2-based FPU support, which acompilercan use for optimization. However, applications that regularly handle integers wider than 32 bits, such as cryptographic algorithms, will need a rewrite of the code handling the huge integers in order to take advantage of the 64-bit registers.

Legacy mode

Legacy mode is the mode that the processor is in when it is not in long mode.In this mode, the processor acts like an older x86 processor, and only 16-bit and 32-bit code can be executed. Legacy mode allows for a maximum of 32 bit virtual addressing which limits the virtual address space to 4 GiB.64-bit programs cannot be run from legacy mode.

Protected mode

Protected modeis made into a submode of legacy mode.It is the submode that 32-bit operating systems and 16-bit protected mode operating systems operate in when running on an x86-64 CPU.

Real mode

Real modeis the initial mode of operation when the processor is initialized, and is a submode of legacy mode. It is backwards compatible with the originalIntel 8086andIntel 8088processors. Real mode is primarily used today by operating system bootloaders, which are required by the architecture to configurevirtual memory detailsbefore transitioning to higher modes. This mode is also used by any operating system that needs to communicate with the system firmware with a traditionalBIOS-style interface.

Intel 64

Intel 64is Intel's implementation of x86-64, used and implemented in various processors made by Intel.

History

Historically, AMD has developed and produced processors with instruction sets patterned after Intel's original designs, but with x86-64, roles were reversed: Intel found itself in the position of adopting theISAthat AMD created as an extension to Intel's own x86 processor line.

Intel's project was originallycodenamedYamhill(after theYamhill Riverin Oregon's Willamette Valley). After several years of denying its existence, Intel announced at the February 2004IDFthat the project was indeed underway. Intel's chairman at the time,Craig Barrett,admitted that this was one of their worst-kept secrets.

Intel's name for this instruction set has changed several times. The name used at the IDF wasCT(presumablyforClackamas Technology,another codename from anOregon river); within weeks they began referring to it asIA-32e(forIA-32extensions) and in March 2004 unveiled the "official" nameEM64T(Extended Memory 64 Technology). In late 2006 Intel began instead using the nameIntel 64for its implementation, paralleling AMD's use of the name AMD64.

The first processor to implement Intel 64 was the multi-socket processorXeoncode-namedNoconain June 2004. In contrast, the initial Prescott chips (February 2004) did not enable this feature. Intel subsequently began selling Intel 64-enabled Pentium 4s using the E0 revision of the Prescott core, being sold on the OEM market as the Pentium 4, model F. The E0 revision also adds eXecute Disable (XD) (Intel's name for theNX bit) to Intel 64, and has been included in then current Xeon code-namedIrwindale.Intel's official launch of Intel 64 (under the name EM64T at that time) in mainstream desktop processors was the N0 stepping Prescott-2M.

The first Intelmobile processorimplementing Intel 64 is theMeromversion of theCore 2processor, which was released on July 27, 2006. None of Intel's earlier notebook CPUs (Core Duo,Pentium M,Celeron M,Mobile Pentium 4) implement Intel 64.

Implementations

Intel's processors implementing the Intel64 architecture include thePentium 4F-series/5x1 series, 506, and 516,Celeron Dmodels 3x1, 3x6, 355, 347, 352, 360, and 365 and all laterCelerons,all models ofXeonsince "Nocona",all models ofPentium Dual-Coreprocessors since "Merom-2M",theAtom230, 330, D410, D425, D510, D525, N450, N455, N470, N475, N550, N570, N2600 and N2800, all versions of thePentium D,Pentium Extreme Edition,Core 2,Core i9,Core i7,Core i5,andCore i3processors, and theXeon Phi7200 series processors.

X86S

X86S is a simplification of x86-64 proposed by Intel in May 2023 for their "Intel 64" products.The new architecture would remove support for 16-bit and 32-bit operating systems, while 32-bit programs will still run under a 64-bit OS. A CPU would no longer havelegacy mode,and start directly in 64-bitlong mode.There will be a way to switch to5-level pagingwithout going through the unpaged mode. Specific removed features include:

• Segmentation gates
• 32-bit ring 0
  • VT-x will no longer emulate this feature
• Rings 1 and 2
• Ring 3 I/O port (IN/OUT) access; seeport-mapped I/O
• String port I/O (INS/OUTS)
• Real mode(includinghuge real mode), 16-bit protected mode, VM86
• 16-bit addressing mode
  • VT-x will no longer provide unrestricted mode
• 8259support; the onlyAPICsupported would be X2APIC
• Some unused operating system mode bits
• 16-bit and 32-bit StartupIPI(SIPI)

Intel believes the change follows logically after the removal of theA20 gatein 2008 and the removal of 16-bit and 32-bit OS support in Intel firmware in 2020. Support for legacy operating systems would be accomplished viahardware-accelerated virtualizationand/orring 0emulation.

Advanced Performance Extensions

Main article:X86 § APX (Advanced Performance Extensions)

Advanced Performance Extensions is a 2023 Intel proposal for new instructions and an additional 16 general-purpose registers.

VIA's x86-64 implementation

VIA Technologiesintroduced their first implementation of the x86-64 architecture in 2008 after five years of development by its CPU division,Centaur Technology. Codenamed "Isaiah", the 64-bit architecture was unveiled on January 24, 2008,and launched on May 29 under theVIA Nanobrand name.

The processor supports a number of VIA-specific x86 extensions designed to boost efficiency in low-power appliances. It is expected that the Isaiah architecture will be twice as fast in integer performance and four times as fast infloating-pointperformance as the previous-generationVIA Estherat an equivalentclock speed.Power consumption is also expected to be on par with the previous-generation VIA CPUs, withthermal design powerranging from 5 W to 25 W. Being a completely new design, the Isaiah architecture was built with support for features like the x86-64 instruction set andx86 virtualizationwhich were unavailable on its predecessors, theVIA C7line, while retaining their encryption extensions.

Microarchitecture levels

In 2020, through a collaboration between AMD, Intel,Red Hat,andSUSE,three microarchitecture levels (or feature levels) on top of the x86-64 baseline were defined: x86-64-v2, x86-64-v3, and x86-64-v4.These levels define specific features that can be targeted by programmers to provide compile-time optimizations. The features exposed by each level are as follows:

CPU microarchitecture levels

Level name	CPU features	Example instruction	Supported processors
(baseline) also as: x86-64-v1	CMOV	cmov	baseline for all x86-64 CPUs matches the common capabilities between the 2003 AMDAMD64and the 2004 IntelEM64Tinitial implementations in the AMDK8and the IntelPrescottprocessor families
	CX8	cmpxchg8b
	FPU	fld
	FXSR	fxsave
	MMX	emms
	OSFXSR	fxsave
	SCE	syscall
	SSE	cvtss2si
	SSE2	cvtpi2pd
x86-64-v2	CMPXCHG16B	cmpxchg16b	IntelNehalemand newer Intel "big" cores Intel (Atom)Silvermontand newer Intel "small" cores AMDBulldozerand newer AMD "big" cores AMDJaguar VIANanoandEden "C" features match the 2008 Intel Nehalem architecture, excluding Intel-specific instructions
	LAHF-SAHF	lahf
	POPCNT	popcnt
	SSE3	addsubpd
	SSE4_1	blendpd
	SSE4_2	pcmpestri
	SSSE3	pshufb
x86-64-v3	AVX	vzeroall	IntelHaswelland newer Intel "big" cores (AVX2 enabled models only) Intel (Atom)Gracemontand newer Intel "small" cores AMDExcavatorand newer AMD "big" cores QEMUemulation (as of version 7.2) features match the 2013 Intel Haswell architecture, excluding Intel-specific instructions
	AVX2	vpermd
	BMI1	andn
	BMI2	bzhi
	F16C	vcvtph2ps
	FMA	vfmadd132pd
	LZCNT	lzcnt
	MOVBE	movbe
	OSXSAVE	xgetbv
x86-64-v4	AVX512F	kmovw	IntelSkylakeand newer Intel "big" cores (AVX512 enabled models only) AMDZen 4and newer AMD cores features match the 2017 Intel Skylake-X architecture, excluding Intel-specific instructions
	AVX512BW	vdbpsadbw
	AVX512CD	vplzcntd
	AVX512DQ	vpmullq
	AVX512VL	—

The x86-64 microarchitecture feature levels can also be found as AMD64-v1, AMD64-v2.. or AMD64_v1.. in settings where the "AMD64" nomenclature is used. These are used as synonyms with the x86-64-vX nomenclature and are thus functionally identical. E.g. the Go language documentation or the Fedora linux distribution.

All levels include features found in the previous levels. Instruction set extensions not concerned with general-purpose computation, includingAES-NIandRDRAND,are excluded from the level requirements.

Differences between AMD64 and Intel 64

Although nearly identical, there are some differences between the two instruction sets in the semantics of a few seldom used machine instructions (or situations), which are mainly used forsystem programming.Compilers generally produceexecutables(i.e.machine code) that avoid any differences, at least for ordinaryapplication programs.This is therefore of interest mainly to developers of compilers, operating systems and similar, which must deal with individual and special system instructions.

Recent implementations

• Intel 64'sBSFandBSRinstructions act differently than AMD64's when the source is zero and the operand size is 32 bits. The processor sets the zero flag and leaves the upper 32 bits of the destination undefined.Note that Intel documents that the destination register has an undefined value in this case, but in practice in silicon implements the same behaviour as AMD (destination unmodified). The separate claim about maybe not preserving bits in the upper 32 has not been verified, but has only been ruled out for Core 2 and Skylake,not all Intel microarchitectures like 64-bit Pentium 4 or low-power Atom.
• AMD64 requires a different microcode update format and control MSRs (model-specific registers), while Intel 64 implementsmicrocodeupdate unchanged from their 32-bit only processors.
• Intel 64 lacks some MSRs that are considered architectural in AMD64. These includeSYSCFG,TOP_MEM,andTOP_MEM2.
• Intel 64 allowsSYSCALL/SYSRETonly in 64-bit mode (not in compatibility mode),and allowsSYSENTER/SYSEXITin both modes.AMD64 lacksSYSENTER/SYSEXITin both sub-modes oflong mode.
• In 64-bit mode, near branches with the 66H (operand size override) prefix behave differently. Intel 64 ignores this prefix: the instruction has a 32-bit sign extended offset, and instruction pointer is not truncated. AMD64 uses a 16-bit offset field in the instruction, and clears the top 48 bits of instruction pointer.
• On Intel 64 but not AMD64, theREX.Wprefix can be used with the far-pointer instructions (LFS,LGS,LSS,JMP FAR,CALL FAR) to increase the size of theirfar pointerargument to 80 bits (64-bit offset + 16-bit segment).
• When theMOVSXDinstruction is executed with a memory source operand and an operand-size of 16 bits, the memory operand will be accessed with a 16-bit read on Intel 64, but a 32-bit read on AMD64.
• TheFCOMI/FCOMIP/FUCOMI/FUCOMIP(x87 floating-point compare) instructions will clear the OF, SF and AF bits ofEFLAGSon Intel 64, but leave these flag bits unmodified on AMD64.
• For theVMASKMOVPS/VMASKMOVPD/VPMASKMOVD/VPMASKMOVQ(AVX/AVX2 masked move to/from memory) instructions, Intel 64 architecturally guarantees that the instructions will not cause memory faults (e.g. page-faults and segmentation-faults) for any zero-masked lanes, while AMD64 does not provide such a guarantee.
• Intel 64 lacks the ability to save and restore a reduced (and thus faster) version of thefloating-pointstate (involving theFXSAVEandFXRSTORinstructions).
• AMD processors ever sinceOpteronRev. E andAthlon 64Rev. D have reintroduced limited support for segmentation, via the Long Mode Segment Limit Enable (LMSLE) bit, to easevirtualizationof 64-bit guests.LMLSE support was removed in the Zen 3 processor.
• When returning to a non-canonical address usingSYSRET,AMD64 processors execute the general protection fault handler in privilege level 3,while on Intel 64 processors it is executed in privilege level 0.
• The ordering guarantees provided by some memory ordering instructions such asLFENCEandMFENCEdiffer between Intel 64 and AMD64:
  • LFENCEis dispatch-serializing (enabling it to be used as aspeculationfence) on Intel 64 but is not architecturally guaranteed to be dispatch-serializing on AMD64.
  • MFENCEis a fully serializing instruction (including instruction fetch serialization) on AMD64 but not Intel 64.

Older implementations

• The AMD64 processors prior to Revision F(distinguished by the switch fromDDRtoDDR2memory and new socketsAM2,FandS1) of 2006 lacked theCMPXCHG16Binstruction, which is an extension of theCMPXCHG8Binstruction present on most post-80486processors. Similar toCMPXCHG8B,CMPXCHG16Ballows foratomic operationson octa-words (128-bit values). This is useful for parallel algorithms that usecompare and swapon data larger than the size of a pointer, common inlock-free and wait-free algorithms.WithoutCMPXCHG16Bone must use workarounds, such as acritical sectionor alternative lock-free approaches.Its absence also prevents 64-bitWindowsprior to Windows 8.1 from having auser-modeaddress space larger than 8TiB.The 64-bit version ofWindows 8.1requires the instruction.
• Early AMD64 and Intel 64 CPUs lackedLAHFandSAHFinstructions in 64-bit mode. AMD introduced these instructions (also in 64-bit mode) with their90 nm(revision D) processors, starting with Athlon 64 in October 2004.Intel introduced the instructions in October 2005 with the 0F47h and later revisions ofNetBurst.The 64-bit version of Windows 8.1 requires this feature.
• Early Intel CPUs with Intel 64 also lack theNX bitof the AMD64 architecture. It was added in the stepping E0 (0F41h) Pentium 4 in October 2004.This feature is required by all versions of Windows 8.
• Early Intel 64 implementations had a 36-bit (64 GiB) physical addressing of memory while original AMD64 implementations had a 40-bit (1TiB) physical addressing. Intel used the 40-bit physical addressing first on Xeon MP (Potomac), launched on 29 March 2005.The difference is not a difference of the user-visible ISAs. In 2007AMD 10h-based Opteron was the first to provide a 48-bit (256 TiB) physical address space.Intel 64's physical addressing was extended to 44 bits (16 TiB) in Nehalem-EX in 2010and to 46 bits (64 TiB) in Sandy Bridge E in 2011.With the Ice Lake 3rd gen Xeon Scalable processors, Intel increased the virtual addressing to 57 bits (128PiB) and physical to 52 bits (4 PiB) in 2021, necessitating a5-level paging.The following year AMD64 added the same in 4th generationEPYC(Genoa).Non-server CPUs retain smaller address spaces for longer.

Adoption

An area chart showing the representation of different families of microprocessors in the TOP500 supercomputer ranking list, from 1993 to 2020

Insupercomputerstracked byTOP500,the appearance of 64-bit extensions for the x86 architecture enabled 64-bit x86 processors by AMD and Intel to replace most RISC processor architectures previously used in such systems (includingPA-RISC,SPARC,Alphaand others), as well as 32-bit x86, even though Intel itself initially tried unsuccessfully to replace x86 with a new incompatible 64-bit architecture in theItaniumprocessor.

As of 2023,aHPEEPYC-based supercomputer calledFrontieris number one. The first ARM-based supercomputer appeared on the list in 2018and, in recent years, non-CPU architecture co-processors (GPGPU) have also played a big role in performance. Intel'sXeon Phi "Knights Corner"coprocessors, which implement a subset of x86-64 with some vector extensions,are also used, along with x86-64 processors, in theTianhe-2supercomputer.

Operating system compatibility and characteristics

The following operating systems and releases support the x86-64 architecture inlong mode.

BSD

DragonFly BSD

Preliminary infrastructure work was started in February 2004 for a x86-64 port.This development later stalled. Development started again during July 2007 and continued duringGoogle Summer of Code2008 and SoC 2009.The first official release to contain x86-64 support was version 2.4.

FreeBSD

FreeBSDfirst added x86-64 support under the name "amd64" as an experimental architecture in 5.1-RELEASE in June 2003. It was included as a standard distribution architecture as of 5.2-RELEASE in January 2004. Since then, FreeBSD has designated it as a Tier 1 platform. The 6.0-RELEASE version cleaned up some quirks with running x86 executables under amd64, and most drivers work just as they do on the x86 architecture. Work is currently being done to integrate more fully the x86application binary interface(ABI), in the same manner as the Linux 32-bit ABI compatibility currently works.

NetBSD

x86-64 architecture support was first committed to theNetBSDsource tree on June 19, 2001. As of NetBSD 2.0, released on December 9, 2004,NetBSD/amd64is a fully integrated and supported port. 32-bit code is still supported in 64-bit mode, with a netbsd-32 kernel compatibility layer for 32-bit syscalls. The NX bit is used to provide non-executable stack and heap with per-page granularity (segment granularity being used on 32-bit x86).

OpenBSD

OpenBSDhas supported AMD64 since OpenBSD 3.5, released on May 1, 2004. Complete in-tree implementation of AMD64 support was achieved prior to the hardware's initial release because AMD had loaned several machines for the project'shackathonthat year. OpenBSD developers have taken to the platform because of its support for theNX bit,which allowed for an easy implementation of theW^Xfeature.

The code for the AMD64 port of OpenBSD also runs on Intel 64 processors which contains cloned use of the AMD64 extensions, but since Intel left out the page table NX bit in early Intel 64 processors, there is no W^X capability on those Intel CPUs; later Intel 64 processors added the NX bit under the name "XD bit".Symmetric multiprocessing(SMP) works on OpenBSD's AMD64 port, starting with release 3.6 on November 1, 2004.

DOS

It is possible to enterlong modeunderDOSwithout a DOS extender,but the user must return to real mode in order to call BIOS or DOS interrupts.

It may also be possible to enterlong modewith aDOS extendersimilar toDOS/4GW,but more complex since x86-64 lacksvirtual 8086 mode.DOS itself is not aware of that, and no benefits should be expected unless running DOS in an emulation with an adequate virtualization driver backend, for example: the mass storage interface.

Linux

See also:Comparison of Linux distributions § Instruction set architecture support

Linuxwas the first operating system kernel to run the x86-64 architecture inlong mode,starting with the 2.4 version in 2001 (preceding the hardware's availability).Linux also provides backward compatibility for running 32-bit executables. This permits programs to be recompiled into long mode while retaining the use of 32-bit programs. Current Linux distributions ship with x86-64-native kernels anduserlands.Some, such asArch Linux,SUSE,Mandriva,andDebian,allow users to install a set of 32-bit components and libraries when installing off a 64-bit distribution medium, thus allowing most existing 32-bit applications to run alongside the 64-bit OS.

x32 ABI(Application Binary Interface), introduced in Linux 3.4, allows programs compiled for the x32 ABI to run in the 64-bit mode of x86-64 while only using 32-bit pointers and data fields. Though this limits the program to a virtual address space of 4 GiB it also decreases the memory footprint of the program and in some cases can allow it to run faster.

64-bit Linux allows up to 128TiBof virtual address space for individual processes, and can address approximately 64 TiB of physical memory, subject to processor and system limitations,or up to 128 PiB (virtual) and 4 PiB (physical) with 5-level paging enabled.

macOS

Mac OS X 10.4.7 and higher versions ofMac OS X 10.4run 64-bit command-line tools using the POSIX and math libraries on 64-bit Intel-based machines, just as all versions of Mac OS X 10.4 and 10.5 run them on 64-bit PowerPC machines. No other libraries or frameworks work with 64-bit applications in Mac OS X 10.4. The kernel, and all kernel extensions, are 32-bit only.

Mac OS X 10.5supports 64-bit GUI applications usingCocoa,Quartz,OpenGL,andX11on 64-bit Intel-based machines, as well as on 64-bitPowerPCmachines. All non-GUI libraries and frameworks also support 64-bit applications on those platforms. The kernel, and all kernel extensions, are 32-bit only.

Mac OS X 10.6is the first version ofmacOSthat supports a 64-bitkernel.However, not all 64-bit computers can run the 64-bit kernel, and not all 64-bit computers that can run the 64-bit kernel will do so by default. The 64-bit kernel, like the 32-bit kernel, supports 32-bit applications; both kernels also support 64-bit applications. 32-bit applications have a virtual address space limit of 4 GiB under either kernel.The 64-bit kernel does not support 32-bitkernel extensions,and the 32-bit kernel does not support 64-bit kernel extensions.

OS X 10.8includes only the 64-bit kernel, but continues to support 32-bit applications; it does not support 32-bit kernel extensions, however.

macOS 10.15includes only the 64-bit kernel and no longer supports 32-bit applications. This removal of support has presented a problem forWineHQ(and the commercial versionCrossOver), as it needs to still be able to run 32-bit Windows applications. The solution, termedwine32on64,was to addthunksthat bring the CPU in and out of 32-bit compatibility mode in the nominally 64-bit application.

macOS uses theuniversal binaryformat to package 32- and 64-bit versions of application and library code into a single file; the most appropriate version is automatically selected at load time. In Mac OS X 10.6, the universal binary format is also used for the kernel and for those kernel extensions that support both 32-bit and 64-bit kernels.

Solaris

See also:illumos

Solaris10 and later releases support the x86-64 architecture.

For Solaris 10, just as with theSPARCarchitecture, there is only one operating system image, which contains a 32-bit kernel and a 64-bit kernel; this is labeled as the "x64/x86" DVD-ROM image. The default behavior is to boot a 64-bit kernel, allowing both 64-bit and existing or new 32-bit executables to be run. A 32-bit kernel can also be manually selected, in which case only 32-bit executables will run. Theisainfocommand can be used to determine if a system is running a 64-bit kernel.

For Solaris 11, only the 64-bit kernel is provided. However, the 64-bit kernel supports both 32- and 64-bit executables, libraries, and system calls.

Windows

x64 editions of Microsoft Windows client and server—Windows XP Professional x64 EditionandWindows Server 2003x64 Edition—were released in March 2005.Internally they are actually the same build (5.2.3790.1830 SP1),as they share the same source base and operating system binaries, so even system updates are released in unified packages, much in the manner as Windows 2000 Professional and Server editions for x86.Windows Vista,which also has many different editions, was released in January 2007.Windows 7was released in July 2009.Windows Server 2008 R2was sold in only x64 and Itanium editions; later versions of Windows Server only offer an x64 edition.

Versions of Windows for x64 prior to Windows 8.1 and Windows Server 2012 R2 offer the following:

• 8 TiB of virtual address space per process, accessible from both user mode and kernel mode, referred to as the user mode address space. An x64 program can use all of this, subject to backing store limits on the system, and provided it is linked with the "large address aware" option, which is present by default.This is a 4096-fold increase over the default 2 GiB user-mode virtual address space offered by 32-bit Windows.
• 8 TiB of kernel mode virtual address space for the operating system.As with the user mode address space, this is a 4096-fold increase over 32-bit Windows versions. The increased space primarily benefits the file system cache and kernel mode "heaps" (non-paged pool and paged pool). Windows only uses a total of 16 TiB out of the 256 TiB implemented by the processors because early AMD64 processors lacked aCMPXCHG16Binstruction.

Under Windows 8.1 and Windows Server 2012 R2, both user mode and kernel mode virtual address spaces have been extended to 128 TiB.These versions of Windows will not install on processors that lack theCMPXCHG16Binstruction.

The following additional characteristics apply to all x64 versions of Windows:

• Ability to run existing 32-bit applications (.exeprograms) and dynamic link libraries (.dlls) usingWoW64if WoW64 is supported on that version. Furthermore, a 32-bit program, if it was linked with the "large address aware" option,can use up to 4 GiB of virtual address space in 64-bit Windows, instead of the default 2 GiB (optional 3 GiB with/3GBboot option and "large address aware" link option) offered by 32-bit Windows.Unlike the use of the/3GBboot option on x86, this does not reduce the kernel mode virtual address space available to the operating system. 32-bit applications can, therefore, benefit from running on x64 Windows even if they are not recompiled for x86-64.
• Both 32- and 64-bit applications, if not linked with "large address aware", are limited to 2 GiB of virtual address space.
• Ability to use up to 128 GiB (Windows XP/Vista), 192 GiB (Windows 7), 512 GiB (Windows 8), 1 TiB (Windows Server 2003), 2 TiB (Windows Server 2008/Windows 10), 4 TiB (Windows Server 2012), or 24 TiB (Windows Server 2016/2019) of physical random access memory (RAM).
• LLP64data model: in C/C++, "int" and "long" types are 32 bits wide, "long long" is 64 bits, while pointers and types derived from pointers are 64 bits wide.
• Kernel mode device drivers must be 64-bit versions; there is no way to run 32-bit kernel mode executables within the 64-bit operating system. User mode device drivers can be either 32-bit or 64-bit.
• 16-bit Windows (Win16) and DOS applications will not run on x86-64 versions of Windows due to the removal of thevirtual DOS machinesubsystem (NTVDM) which relied upon the ability to use virtual 8086 mode. Virtual 8086 mode cannot be entered while running in long mode.
• Full implementation of theNX(No Execute) page protection feature. This is also implemented on recent 32-bit versions of Windows when they are started in PAE mode.
• Instead of FS segment descriptor on x86 versions of theWindows NTfamily, GS segment descriptor is used to point to two operating system defined structures: Thread Information Block (NT_TIB) in user mode and Processor Control Region (KPCR) in kernel mode. Thus, for example, in user modeGS:0is the address of the first member of the Thread Information Block. Maintaining this convention made the x86-64 port easier, but required AMD to retain the function of the FS and GS segments in long mode – even though segmented addressingper seis not really used by any modern operating system.
• Early reports claimed that the operating system scheduler would not save and restore thex87FPU machine state across thread context switches. Observed behavior shows that this is not the case: the x87 state is saved and restored, except for kernel mode-only threads (a limitation that exists in the 32-bit version as well). The most recent documentation available from Microsoft states that the x87/MMX/3DNow!instructions may be used in long mode, but that they are deprecated and may cause compatibility problems in the future.(3DNow! is no longer available on AMD processors, with the exception of thePREFETCHandPREFETCHWinstructions,which are also supported on Intel processors as ofBroadwell.)
• Some components likeJet Database EngineandData Access Objectswill not be ported to 64-bit architectures such as x86-64 and IA-64.
• Microsoft Visual Studiocan compilenative applicationsto target either the x86-64 architecture, which can run only on 64-bit Microsoft Windows, or theIA-32architecture, which can run as a 32-bit application on 32-bit Microsoft Windows or 64-bit Microsoft Windows inWoW64emulation mode.Managed applicationscan be compiled either in IA-32, x86-64 or AnyCPU modes. Software created in the first two modes behave like their IA-32 or x86-64 native code counterparts respectively; When using the AnyCPU mode, however, applications in 32-bit versions of Microsoft Windows run as 32-bit applications, while they run as a 64-bit application in 64-bit editions of Microsoft Windows.

Video game consoles

ThePlayStation 4andXbox Oneuse AMD x86-64 processors based on theJaguarmicroarchitecture.Firmware and games are written in x86-64 code; no legacy x86 code is involved. ThePlayStation 5andXbox Series X/Suse AMD x86-64 processors based on theZen 2microarchitecture.TheSteam Deckuses a custom AMD x86-64accelerated processing unit(APU) based on the Zen 2 microarchitecture.

Industry naming conventions

Since AMD64 and Intel 64 are substantially similar, many software and hardware products use one vendor-neutral term to indicate their compatibility with both implementations. AMD's original designation for this processor architecture, "x86-64", is still used for this purpose,as is the variant "x86_64".Other companies, such asMicrosoftandSun Microsystems/Oracle Corporation,use the contraction "x64" in marketing material.

The termIA-64refers to theItaniumprocessor, and should not be confused with x86-64, as it is a completely different instruction set.

Many operating systems and products, especially those that introduced x86-64 support prior to Intel's entry into the market, use the term "AMD64" or "amd64" to refer to both AMD64 and Intel 64.

• amd64
  • MostBSDsystems such asFreeBSD,MidnightBSD,NetBSDandOpenBSDrefer to both AMD64 and Intel 64 under the architecture name "amd64".
  • SomeLinux distributionssuch asDebian,Ubuntu,Gentoo Linuxrefer to both AMD64 and Intel 64 under the architecture name "amd64".
  • Microsoft Windows's x64 versions use the AMD64 moniker internally to designate various components which use or are compatible with this architecture. For example, theenvironment variablePROCESSOR_ARCHITECTURE is assigned the value "AMD64" as opposed to "x86" in 32-bit versions, and the system directory on a Windows x64 Edition installation CD-ROM is named "AMD64", in contrast to "i386" in 32-bit versions.
  • Sun'sSolaris'sisalistcommand identifies both AMD64- and Intel 64-based systems as "amd64".
  • Java Development Kit(JDK): the name "amd64" is used in directory names containing x86-64 files.
• x86_64
  • TheLinux kerneland theGNU Compiler Collectionrefers to 64-bit architecture as "x86_64".
  • Some Linux distributions, such asFedora,openSUSE,Arch Linux,Gentoo Linuxrefer to this 64-bit architecture as "x86_64".
  • ApplemacOSrefers to 64-bit architecture as "x86-64" or "x86_64", as seen in the Terminal commandarchand in their developer documentation.
  • Breaking with most other BSD systems,DragonFly BSDrefers to 64-bit architecture as "x86_64".
  • Haikurefers to 64-bit architecture as "x86_64".

Licensing

x86-64/AMD64 was solely developed by AMD. Until April 2021 when the relevant patents expired, AMD held patents on techniques used in AMD64;those patents had to be licensed from AMD in order to implement AMD64. Intel entered into a cross-licensing agreement with AMD, licensing to AMD their patents on existing x86 techniques, and licensing from AMD their patents on techniques used in x86-64.In 2009, AMD and Intel settled several lawsuits and cross-licensing disagreements, extending their cross-licensing agreements.

See also

• AMD Generic Encapsulated Software Architecture(AGESA)
• Speculative execution CPU vulnerabilities

External links

• AMD Developer Guides, Manuals & ISA Documents
• x86-64: Extending the x86 architecture to 64-bits– technical talk by the architect of AMD64 (video archive), andsecond talk by the same speaker(video archive)
• AMD's "Enhanced Virus Protection"
• Intel tweaks EM64T for full AMD64 compatibility
• Analyst: Intel Reverse-Engineered AMD64
• Early report of differences between Intel IA32e and AMD64
• Porting to 64-bit GNU/Linux Systems,by Andreas Jaeger fromGCC Summit2003. An excellent paper explaining almost all practical aspects for a transition from 32-bit to 64-bit.
• Intel 64 Architecture
• Intel Software Network: "64 bits"
• TurboIRC.COM tutorials, including examples of how to of enter protected and long mode the raw way from DOS
• Seven Steps of Migrating a Program to a 64-bit System
• Memory Limits for Windows Releases