CMOS

For other uses, seeCMOS (disambiguation).

CMOS inverter (aNOT logic gate)

Complementary metal–oxide–semiconductor(CMOS,pronounced "sea-moss",/siːmɑːs/,/-ɒs/) is a type ofmetal–oxide–semiconductor field-effect transistor(MOSFET)fabrication processthat uses complementary and symmetrical pairs ofp-typeandn-typeMOSFETs for logic functions.CMOS technology is used for constructingintegrated circuit(IC) chips, includingmicroprocessors,microcontrollers,memory chips(includingCMOS BIOS), and otherdigital logiccircuits. CMOS technology is also used foranalog circuitssuch asimage sensors(CMOS sensors),data converters,RF circuits(RF CMOS), and highly integratedtransceiversfor many types of communication.

In 1948, Bardeen and Brattain patented an insulated-gate transistor (IGFET) with an inversion layer. Bardeen's concept forms the basis of CMOS technology today. The CMOS process was presented byFairchild Semiconductor'sFrank WanlassandChih-Tang Sahat theInternational Solid-State Circuits Conferencein 1963. Wanlass later filedUS patent 3,356,858for CMOS circuitry and it was granted in 1967.RCAcommercialized the technology with the trademark "COS-MOS" in the late 1960s, forcing other manufacturers to find another name, leading to "CMOS" becoming the standard name for the technology by the early 1970s. CMOS overtookNMOS logicas the dominant MOSFET fabrication process forvery large-scale integration(VLSI) chips in the 1980s, also replacing earliertransistor–transistor logic(TTL) technology. CMOS has since remained the standard fabrication process for MOSFETsemiconductor devicesin VLSI chips. As of 2011,99% of IC chips, including mostdigital,analogandmixed-signalICs, were fabricated using CMOS technology.

Two important characteristics of CMOS devices are highnoise immunityand low staticpower consumption. Since onetransistorof the MOSFET pair is always off, the series combination draws significant power only momentarily during switching between on and off states. Consequently, CMOS devices do not produce as muchwaste heatas other forms of logic, likeNMOS logicortransistor–transistor logic(TTL), which normally have some standing current even when not changing state. These characteristics allow CMOS to integrate a high density of logic functions on a chip. It was primarily for this reason that CMOS became the most widely used technology to be implemented in VLSI chips.

The phrase "metal–oxide–semiconductor" is a reference to the physical structure of MOSfield-effect transistors,having ametal gateelectrode placed on top of an oxide insulator, which in turn is on top of asemiconductor material.Aluminiumwas once used but now the material ispolysilicon.Other metal gates have made a comeback with the advent ofhigh-κ dielectricmaterials in the CMOS process, as announced by IBM and Intel for the45 nanometernode and smaller sizes.

History

Further information:MOSFETandTransistor density

1957, Diagram of one of the SiO2 transistor devices made by Frosch and Derrick

The principle of complementary symmetry was first introduced byGeorge Sziklaiin 1953 who then discussed several complementary bipolar circuits.Paul Weimer,also atRCA,invented in 1962thin-film transistor(TFT) complementary circuits, a close relative of CMOS. He invented complementaryflip-flopand inverter circuits, but did no work in a more complex complementary logic. He was the first person able to put p-channel and n-channel TFTs in a circuit on the same substrate. Three years earlier,John T. Wallmarkand Sanford M. Marcus published a variety of complex logic functions implemented as integrated circuits usingJFETs,including complementary memory circuits. Frank Wanlass was familiar with work done by Weimer at RCA.

In 1955,Carl Froschand Lincoln Derick accidentally grew a layer of silicon dioxide over the silicon wafer, for which they observed surface passivation effects.By 1957 Frosch and Derrick, using masking and predeposition, were able to manufacture silicon dioxide transistors and showed that silicon dioxide insulated, protected silicon wafers and prevented dopants from diffusing into the wafer.J.R. Ligenza and W.G. Spitzer studied the mechanism of thermally grown oxides and fabricated a high quality Si/SiO₂stack in 1960.

Simulation of formation of inversion channel (electron density) and attainment ofthreshold voltage(IV) in a nanowire MOSFET. Threshold voltage for this device lies around 0.45 V.

Following this research,Mohamed AtallaandDawon Kahngproposed a silicon MOS transistor in 1959and successfully demonstrated a working MOS device with their Bell Labs team in 1960.Their team included E. E. LaBate and E. I. Povilonis who fabricated the device; M. O. Thurston, L. A. D'Asaro, and J. R. Ligenza who developed the diffusion processes, and H. K. Gummel and R. Lindner who characterized the device.There were originally two types of MOSFET logic,PMOS(p-typeMOS) andNMOS(n-typeMOS).Both types were developed by Frosch and Derrick in 1957 at Bell Labs.

In 1948, Bardeen and Brattain patented the progenitor of MOSFET, an insulated-gate FET (IGFET) with an inversion layer. Bardeen's patent, and the concept of an inversion layer, forms the basis of CMOS technology today.A new type of MOSFET logic combining both the PMOS and NMOS processes was developed, called complementary MOS (CMOS), by Chih-Tang Sah andFrank Wanlassat Fairchild. In February 1963, they published the invention in aresearch paper.In both the research paper and thepatentfiled by Wanlass, the fabrication of CMOS devices was outlined, on the basis ofthermal oxidationof a silicon substrate to yield a layer ofsilicon dioxidelocated between the drain contact and the source contact.

CMOS was commercialised byRCAin the late 1960s. RCA adopted CMOS for the design ofintegrated circuits(ICs), developing CMOS circuits for anAir Forcecomputer in 1965 and then a 288-bitCMOSSRAMmemory chip in 1968.RCA also used CMOS for its4000-series integrated circuitsin 1968, starting with a 20μmsemiconductor manufacturing processbefore gradually scaling to a10 μm processover the next several years.

CMOS technology was initially overlooked by the Americansemiconductor industryin favour of NMOS, which was more powerful at the time. However, CMOS was quickly adopted and further advanced by Japanese semiconductor manufacturers due to its low power consumption, leading to the rise of the Japanese semiconductor industry.Toshibadeveloped C²MOS (Clocked CMOS), a circuit technology with lowerpower consumptionand faster operating speed than ordinary CMOS, in 1969. Toshiba used its C²MOS technology to develop alarge-scale integration(LSI) chip forSharp's Elsi MiniLEDpocket calculator,developed in 1971 and released in 1972.Suwa Seikosha(nowSeiko Epson) began developing a CMOS IC chip for aSeikoquartz watchin 1969, and began mass-production with the launch of theSeikoAnalog Quartz 38SQW watch in 1971.The first mass-produced CMOS consumer electronic product was theHamiltonPulsar "Wrist Computer" digital watch, released in 1970.Due to low power consumption, CMOS logic has been widely used forcalculatorsandwatchessince the 1970s.

Theearliest microprocessorsin the early 1970s were PMOS processors, which initially dominated the earlymicroprocessorindustry. By the late 1970s, NMOS microprocessors had overtaken PMOS processors.CMOS microprocessors were introduced in 1975, with theIntersil 6100,and RCACDP 1801.However, CMOS processors did not become dominant until the 1980s.

CMOS was initially slower thanNMOS logic,thus NMOS was more widely used for computers in the 1970s.TheIntel5101 (1kbSRAM) CMOS memory chip (1974) had anaccess timeof 800ns,whereas the fastest NMOS chip at the time, the Intel 2147 (4kb SRAM)HMOSmemory chip (1976), had an access time of 55/70ns.In 1978, aHitachiresearch team led by Toshiaki Masuhara introduced the twin-well Hi-CMOS process, with its HM6147 (4kb SRAM) memory chip, manufactured with a3 μm process.The Hitachi HM6147 chip was able to match the performance (55/70ns access) of the Intel 2147 HMOS chip, while the HM6147 also consumed significantly less power (15mA) than the 2147 (110mA). With comparable performance and much less power consumption, the twin-well CMOS process eventually overtook NMOS as the most commonsemiconductor manufacturing processfor computers in the 1980s.

In the 1980s, CMOS microprocessors overtook NMOS microprocessors.NASA'sGalileospacecraft, sent to orbitJupiterin 1989, used theRCA 1802CMOS microprocessor due to low power consumption.

Intel introduced a1.5 μm processfor CMOSsemiconductor device fabricationin 1983.In the mid-1980s,Bijan DavariofIBMdeveloped high-performance, low-voltage,deep sub-micronCMOS technology, which enabled the development of faster computers as well asportable computersand battery-poweredhandheld electronics.In 1988, Davari led an IBM team that demonstrated a high-performance250 nanometerCMOS process.

Fujitsucommercialized a 700nmCMOS process in 1987,and then Hitachi,Mitsubishi Electric,NECand Toshiba commercialized500nmCMOS in 1989.In 1993,Sonycommercialized a350nmCMOS process, while Hitachi and NEC commercialized250nmCMOS. Hitachi introduced a160nmCMOS process in 1995, then Mitsubishi introduced 150nm CMOS in 1996, and thenSamsung Electronicsintroduced 140nm in 1999.

In 2000,Gurtej Singh Sandhuand Trung T. Doan atMicron Technologyinventedatomic layer depositionHigh-κ dielectricfilms,leading to the development of a cost-effective90 nmCMOS process.Toshiba and Sony developed a65 nmCMOS process in 2002,and thenTSMCinitiated the development of45 nmCMOS logic in 2004.The development of pitchdouble patterningby Gurtej Singh Sandhu at Micron Technology led to the development of30nmclass CMOS in the 2000s.

CMOS is used in most modern LSI andVLSIdevices.As of 2010,CPUswith the bestperformance per watteach year have been CMOSstatic logicsince 1976.As of 2019, planar CMOS technology is still the most common form of semiconductor device fabrication, but is gradually being replaced by non-planarFinFETtechnology, which is capable of manufacturingsemiconductor nodessmaller than20nm.

Technical details

Further information:Semiconductor manufacturing processes

"CMOS" refers to both a particular style of digital circuitry design and the family of processes used to implement that circuitry on integrated circuits (chips). CMOS circuitry dissipatesless powerthanlogic familieswith resistive loads. Since this advantage has increased and grown more important, CMOS processes and variants have come to dominate, thus the vast majority of modern integrated circuit manufacturing is on CMOS processes.CMOS logic consumes around one seventh the power ofNMOS logic,and about 10 million times less power than bipolartransistor-transistor logic(TTL).

CMOS circuits use a combination of p-type and n-typemetal–oxide–semiconductor field-effect transistor(MOSFETs) to implementlogic gatesand other digital circuits. Although CMOS logic can be implemented with discrete devices for demonstrations, commercial CMOS products are integrated circuits composed of up to billions of transistors of both types, on a rectangular piece ofsiliconof often between 10 and 400 mm².

CMOS always uses allenhancement-modeMOSFETs (in other words, a zero gate-to-source voltage turns the transistor off).

Inversion

CMOS circuits are constructed in such a way that allP-type metal–oxide–semiconductor(PMOS) transistors must have either an input from the voltage source or from another PMOS transistor. Similarly, allNMOStransistors must have either an input from ground or from another NMOS transistor. The composition of a PMOS transistor creates lowresistancebetween its source and drain contacts when a low gatevoltageis applied and high resistance when a high gate voltage is applied. On the other hand, the composition of an NMOS transistor creates high resistance between source and drain when a low gate voltage is applied and low resistance when a high gate voltage is applied. CMOS accomplishes current reduction by complementing every nMOSFET with a pMOSFET and connecting both gates and both drains together. A high voltage on the gates will cause the nMOSFET to conduct and the pMOSFET not to conduct, while a low voltage on the gates causes the reverse. This arrangement greatly reduces power consumption and heat generation. However, during the switching time, both pMOS and nMOS MOSFETs conduct briefly as the gate voltage transitions from one state to another. This induces a brief spike in power consumption and becomes a serious issue at high frequencies.

Static CMOS inverter.V_ddandV_ssstand fordrain and source,respectively.

The adjacent image shows what happens when an input is connected to both a PMOS transistor (top of diagram) and an NMOS transistor (bottom of diagram). Vdd is some positive voltage connected to a power supply and Vss is ground. A is the input and Q is the output.

When the voltage of A is low (i.e. close to Vss), the NMOS transistor's channel is in a high resistance state, disconnecting Vss from Q. The PMOS transistor's channel is in a low resistance state, connecting Vdd to Q. Q, therefore, registers Vdd.

On the other hand, when the voltage of A is high (i.e. close to Vdd), the PMOS transistor is in a high resistance state, disconnecting Vdd from Q. The NMOS transistor is in a low resistance state, connecting Vss to Q. Now, Q registers Vss.

In short, the outputs of the PMOS and NMOS transistors are complementary such that when the input is low, the output is high, and when the input is high, the output is low. No matter what the input is, the output is never left floating (charge is never stored due to wire capacitance and lack of electrical drain/ground). Because of this behavior of input and output, the CMOS circuit's output is the inverse of the input.

The transistors' resistances are never exactly equal to zero or infinity, so Q will never exactly equal Vss or Vdd, but Q will always be closer to Vss than A was to Vdd (or vice versa if A were close to Vss). Without this amplification, there would be a very low limit to the number of logic gates that could be chained together in series, and CMOS logic with billions of transistors would be impossible.

Power supply pins

See also:IC power-supply pin

The power supply pins for CMOS are called V_DDand V_SS,or V_CCand Ground(GND) depending on the manufacturer. V_DDand V_SSare carryovers from conventional MOS circuits and stand for thedrainandsourcesupplies.These do not apply directly to CMOS, since both supplies are really source supplies. V_CCand Ground are carryovers fromTTL logicand that nomenclature has been retained with the introduction of the 54C/74C line of CMOS.

Duality

An important characteristic of a CMOS circuit is the duality that exists between its PMOS transistors and NMOS transistors. A CMOS circuit is created to allow a path always to exist from the output to either the power source or ground. To accomplish this, the set of all paths to the voltage source must be thecomplementof the set of all paths to ground. This can be easily accomplished by defining one in terms of the NOT of the other. Due to the logic based onDe Morgan's laws,the PMOS transistors in parallel have corresponding NMOS transistors in series while the PMOS transistors in series have corresponding NMOS transistors in parallel.

Logic

NAND gatein CMOS logic

More complex logic functions such as those involvingANDandOR gatesrequire manipulating the paths between gates to represent the logic. When a path consists of two transistors in series, both transistors must have low resistance to the corresponding supply voltage, modelling an AND. When a path consists of two transistors in parallel, either one or both of the transistors must have low resistance to connect the supply voltage to the output, modelling an OR.

Shown on the right is acircuit diagramof aNAND gatein CMOS logic. If both of the A and B inputs are high, then both the NMOS transistors (bottom half of the diagram) will conduct, neither of the PMOS transistors (top half) will conduct, and a conductive path will be established between the output andV_ss(ground), bringing the output low. If both of the A and B inputs are low, then neither of the NMOS transistors will conduct, while both of the PMOS transistors will conduct, establishing a conductive path between the output andV_dd(voltage source), bringing the output high. If either of the A or B inputs is low, one of the NMOS transistors will not conduct, one of the PMOS transistors will, and a conductive path will be established between the output andV_dd(voltage source), bringing the output high. As the only configuration of the two inputs that results in a low output is when both are high, this circuit implements aNAND(NOT AND) logic gate.

An advantage of CMOS over NMOS logic is that both low-to-high and high-to-low output transitions are fast since the (PMOS) pull-up transistors have low resistance when switched on, unlike the load resistors in NMOS logic. In addition, the output signal swings the fullvoltagebetween the low and high rails. This strong, more nearly symmetric response also makes CMOS more resistant to noise.

SeeLogical effortfor a method of calculating delay in a CMOS circuit.

Example: NAND gate in physical layout

Thephysical layoutof a NAND circuit. The larger regions of N-type diffusion and P-type diffusion are part of the transistors. The two smaller regions on the left are taps to preventlatchup.

Simplified process of fabrication of a CMOS inverter on p-type substrate in semiconductor microfabrication. In step 1,silicon dioxidelayers are formed initially throughthermal oxidationNote: Gate, source and drain contacts are not normally in the same plane in real devices, and the diagram is not to scale.

This example shows aNANDlogic device drawn as a physical representation as it would be manufactured. The physical layout perspective is a "bird's eye view" of a stack of layers. The circuit is constructed on aP-typesubstrate. Thepolysilicon,diffusion, and n-well are referred to as "base layers" and are actually inserted into trenches of the P-type substrate. (See steps 1 to 6 in the process diagram below right) The contacts penetrate an insulating layer between the base layers and the first layer of metal (metal1) making a connection.

The inputs to theNAND(illustrated in green color) are in polysilicon. The transistors (devices) are formed by the intersection of the polysilicon and diffusion; N diffusion for the N device & P diffusion for the P device (illustrated in salmon and yellow coloring respectively). The output ( "out" ) is connected together in metal (illustrated in cyan coloring). Connections between metal and polysilicon or diffusion are made through contacts (illustrated as black squares). Thephysical layoutexample matches the NAND logic circuit given in the previous example.

The N device is manufactured on a P-type substrate while the P device is manufactured in anN-typewell (n-well). A P-type substrate "tap" is connected to V_SSand an N-type n-well tap is connected to V_DDto preventlatchup.

Cross section of two transistors in a CMOS gate, in an N-well CMOS process

Power: switching and leakage

CMOS logic dissipates less power than NMOS logic circuits because CMOS dissipates power only when switching ( "dynamic power" ). On a typicalASICin a modern90 nanometerprocess, switching the output might take 120 picoseconds, and happens once every ten nanoseconds. NMOS logic dissipates power whenever the transistor is on, because there is a current path from V_ddto V_ssthrough the load resistor and the n-type network.

Static CMOS gates are very power efficient because they dissipate nearly zero power when idle. Earlier, the power consumption of CMOS devices was not the major concern while designing chips. Factors like speed and area dominated the design parameters. As the CMOS technology moved below sub-micron levels the power consumption per unit area of the chip has risen tremendously.

Broadly classifying, power dissipation in CMOS circuits occurs because of two components, static and dynamic:

Static dissipation

Both NMOS and PMOS transistors have a gate–sourcethreshold voltage(V_th), below which the current (calledsub thresholdcurrent) through the device will drop exponentially. Historically, CMOS circuits operated at supply voltages much larger than their threshold voltages (V_ddmight have been 5 V, and V_thfor both NMOS and PMOS might have been 700 mV). A special type of the transistor used in some CMOS circuits is thenative transistor,with near zerothreshold voltage.

SiO₂is a good insulator, but at very small thickness levels electrons can tunnel across the very thin insulation; the probability drops off exponentially with oxide thickness. Tunnelling current becomes very important for transistors below 130 nm technology with gate oxides of 20 Å or thinner.

Small reverse leakage currents are formed due to formation of reverse bias between diffusion regions and wells (for e.g., p-type diffusion vs. n-well), wells and substrate (for e.g., n-well vs. p-substrate). In modern process diode leakage is very small compared to sub threshold and tunnelling currents, so these may be neglected during power calculations.

If the ratios do not match, then there might be different currents of PMOS and NMOS; this may lead to imbalance and thus improper current causes the CMOS to heat up and dissipate power unnecessarily. Furthermore, recent studies have shown that leakage power reduces due to aging effects as a trade-off for devices to become slower.

To speed up designs, manufacturers have switched to constructions that have lower voltage thresholds but because of this a modern NMOS transistor with a V_thof 200 mV has a significantsubthreshold leakagecurrent. Designs (e.g. desktop processors) which include vast numbers of circuits which are not actively switching still consume power because of this leakage current. Leakage power is a significant portion of the total power consumed by such designs.Multi-threshold CMOS(MTCMOS), now available from foundries, is one approach to managing leakage power. With MTCMOS, high V_thtransistors are used when switching speed is not critical, while low V_thtransistors are used in speed sensitive paths. Further technology advances that use even thinner gate dielectrics have an additionalleakagecomponent because of currenttunnellingthrough the extremely thin gate dielectric. Usinghigh-κ dielectricsinstead ofsilicon dioxidethat is the conventional gate dielectric allows similar device performance, but with a thicker gate insulator, thus avoiding this current. Leakage power reduction using new material and system designs is critical to sustaining scaling of CMOS.

Dynamic dissipation

Charging and discharging of load capacitances

CMOS circuits dissipate power by charging the various load capacitances (mostly gate and wire capacitance, but also drain and some source capacitances) whenever they are switched. In one complete cycle of CMOS logic, current flows from V_DDto the load capacitance to charge it and then flows from the charged load capacitance (C_L) to ground during discharge. Therefore, in one complete charge/discharge cycle, a total of Q=C_LV_DDis thus transferred from V_DDto ground. Multiply by the switching frequency on the load capacitances to get the current used, and multiply by the average voltage again to get the characteristic switching power dissipated by a CMOS device:$P=0.5CV^{2}f$.

Since most gates do not operate/switch at everyclock cycle,they are often accompanied by a factor$\alpha$,called the activity factor. Now, the dynamic power dissipation may be re-written as$P=\alpha CV^{2}f$.

A clock in a system has an activity factor α=1, since it rises and falls every cycle. Most data has an activity factor of 0.1.If correct load capacitance is estimated on a node together with its activity factor, the dynamic power dissipation at that node can be calculated effectively.

Short-circuit power

Since there is a finite rise/fall time for both pMOS and nMOS, during transition, for example, from off to on, both the transistors will be on for a small period of time in which current will find a path directly from V_DDto ground, hence creating ashort-circuit current,sometimes called acrowbarcurrent. Short-circuit power dissipation increases with the rise and fall time of the transistors.

This form of power consumption became significant in the 1990s as wires on chip became narrower and the long wires became more resistive. CMOS gates at the end of those resistive wires see slow input transitions. Careful design which avoids weakly driven long skinny wires reduces this effect, but crowbar power can be a substantial part of dynamic CMOS power.

Input protection

Parasitic transistors that are inherent in the CMOS structure may be turned on by input signals outside the normal operating range, e.g.electrostatic dischargesorline reflections.The resultinglatch-upmay damage or destroy the CMOS device. Clamp diodes are included in CMOS circuits to deal with these signals. Manufacturers' data sheets specify the maximum permitted current that may flow through the diodes.

Analog CMOS

Further information:CMOS amplifierandMixed-signal integrated circuit

Besides digital applications, CMOS technology is also used inanalogapplications. For example, there are CMOSoperational amplifierICs available in the market.Transmission gatesmay be used as analogmultiplexersinstead of signalrelays.CMOS technology is also widely used forRFcircuits all the way to microwave frequencies, inmixed-signal(analog+digital) applications.

RF CMOS

Main article:RF CMOS

RF CMOS refers toRF circuits(radio frequencycircuits) which are based onmixed-signalCMOS integrated circuittechnology. They are widely used inwireless telecommunicationtechnology. RF CMOS was developed byAsad Abidiwhile working atUCLAin the late 1980s. This changed the way in which RF circuits were designed, leading to the replacement of discretebipolar transistorswith CMOS integrated circuits inradiotransceivers.It enabled sophisticated, low-cost and portableend-userterminals, and gave rise to small, low-cost, low-power and portable units for a wide range of wireless communication systems. This enabled "anytime, anywhere" communication and helped bring about thewireless revolution,leading to the rapid growth of the wireless industry.

Thebaseband processorsand radio transceivers in all modernwireless networkingdevices andmobile phonesare mass-produced using RF CMOS devices.RF CMOS circuits are widely used to transmit and receive wireless signals, in a variety of applications, such assatellitetechnology (such asGPS),bluetooth,Wi-Fi,near-field communication(NFC),mobile networks(such as3Gand4G),terrestrialbroadcast,andautomotiveradarapplications, among other uses.

Examples of commercial RF CMOS chips include Intel'sDECTcordless phone, and802.11(Wi-Fi) chips created byAtherosand other companies.Commercial RF CMOS products are also used forBluetoothandWireless LAN(WLAN) networks.RF CMOS is also used in the radio transceivers for wireless standards such asGSM,Wi-Fi, and Bluetooth, transceivers for mobile networks such as 3G, and remote units inwireless sensor networks(WSN).

RF CMOS technology is crucial to modern wireless communications, including wireless networks andmobile communicationdevices. One of the companies that commercialized RF CMOS technology wasInfineon.Its bulk CMOSRF switchessell over 1billion units annually, reaching a cumulative 5billion units, as of 2018.

Temperature range

Conventional CMOS devices work over a range of −55 °C to +125 °C.

There were theoretical indications as early as August 2008 that silicon CMOS will work down to −233 °C (40K).Functioning temperatures near 40 K have since been achieved using overclocked AMDPhenom IIprocessors with a combination ofliquid nitrogenandliquid heliumcooling.

Silicon carbideCMOS devices have been tested for a year at 500 °C.

Single-electron MOS transistors

Ultra small (L = 20 nm, W = 20 nm) MOSFETs achieve the single-electron limit when operated at cryogenic temperature over a range of −269 °C (4K) to about −258 °C (15K). The transistor displaysCoulomb blockadedue to progressive charging of electrons one by one. The number of electrons confined in the channel is driven by the gate voltage, starting from an occupation of zero electrons, and it can be set to one or many.

See also

• Gate equivalent– Measure of circuit complexity
• HCMOS– Specifications for the 74HC00 IC family
• LVCMOS
• sCMOS– Camera technology

Further reading

See also:List of books about 4000-series integrated circuits

• Bader, S.J.; Lee, H.; Chaudhuri, R.; Huang, S.; Hickman, A.; Molnar, A.; Xing, H.G.; Jena, D.; W. Then, H.; Chowdhury, N.; Palacios, T. (October 2020)."Prospects for Wide Bandgap and Ultrawide Bandgap CMOS Devices"(PDF).IEEE Transactions on Electron Devices.67(10): 4010–20.Bibcode:2020ITED...67.4010B.doi:10.1109/TED.2020.3010471.S2CID221913316.
• Baker, R. Jacob (2010).CMOS: Circuit Design, Layout, and Simulation(3rd ed.). Wiley-IEEE.ISBN978-0-470-88132-3.
• Mead, Carver A.;Conway, Lynn(1980).Introduction to VLSI systems.Addison-Wesley.ISBN0-201-04358-0.
• Veendrick, H.J.M. (2017).Nanometer CMOS ICs: From Basics to ASICs.Springer.doi:10.1007/978-3-319-47597-4.ISBN978-3-319-47595-0.
• Weste, Neil H. E.; Harris, David M. (2010).CMOS VLSI Design: A Circuits and Systems Perspective(4th ed.). Pearson/Addison-Wesley.ISBN978-0-321-54774-3.

External links

• CMOS gate description and interactive illustrations