VHDL

For Verilog HDL, seeVerilog.

VHDL

Paradigm	concurrent,reactive,dataflow
First appeared	1980s
Stable release	IEEE 1076-2019 / 23 December 2019(2019-12-23)
Typing discipline	strong
Filename extensions	.vhd
Website	IEEE VASG
Dialects
VHDL-AMS
Influenced by
Ada,Pascal
Programmable Logic/VHDLat Wikibooks

VHDL source for a signedadder

VHDL(VHSICHardware Description Language) is ahardware description languagethat can model the behavior and structure ofdigital systemsat multiple levels of abstraction, ranging from the system level down to that oflogic gates,for design entry, documentation, and verification purposes. The language was developed for the US militaryVHSICprogram in the 1980s, and has been standardized by theInstitute of Electrical and Electronics Engineers(IEEE) asIEEE Std 1076;the latest version of which isIEEE Std 1076-2019.To modelanalogandmixed-signalsystems, an IEEE-standardized HDL based on VHDL calledVHDL-AMS(officially IEEE 1076.1) has been developed.

History

In 1983, VHDL was originally developed at the behest of theU.S. Department of Defensein order to document the behavior of theASICsthat supplier companies were including in equipment. The standard MIL-STD-454Nin Requirement 64 in section 4.5.1 "ASIC documentation in VHDL" explicitly requires documentation of "Microelectronic Devices" in VHDL.

The idea of being able to simulate the ASICs from the information in this documentation was so obviously attractive thatlogic simulatorswere developed that could read the VHDL files. The next step was the development oflogic synthesistools that read the VHDL and output a definition of the physical implementation of the circuit.

Due to the Department of Defense requiring as much of the syntax as possible to be based on Ada, in order to avoid re-inventing concepts that had already been thoroughly tested in the development of Ada,VHDL borrows heavily from theAda programming languagein both concept andsyntax.

The initial version of VHDL, designed toIEEEstandard IEEE 1076-1987,included a wide range of data types, including numerical (integerandreal), logical (bitandboolean),characterandtime,plusarraysofbitcalledbit_vectorand ofcharactercalledstring.

A problem not solved by this edition, however, was "multi-valued logic", where a signal'sdrive strength(none, weak or strong) and unknown values are also considered. This requiredIEEE standard 1164,which defined the 9-value logic types: scalarstd_logicand its vector versionstd_logic_vector.Being a resolved subtype of itsstd_Ulogicparent type,std_logic-typed signals allow multiple driving for modeling bus structures, whereby the connected resolution function handles conflicting assignments adequately.

The updatedIEEE 1076,in 1993, made the syntax more consistent, allowed more flexibility in naming, extended thecharactertype to allowISO-8859-1printable characters, added thexnoroperator, etc.

Minor changes in the standard (2000 and 2002) added the idea of protected types (similar to the concept of class inC++) and removed some restrictions from port mapping rules.

In addition to IEEE standard 1164, several child standards were introduced to extend functionality of the language. IEEE standard 1076.2 added better handling of real and complex data types. IEEE standard 1076.3 introducedsigned and unsignedtypes to facilitate arithmetical operations on vectors. IEEE standard 1076.1 (known asVHDL-AMS) provided analog and mixed-signal circuit design extensions.

Some other standards support wider use of VHDL, notablyVITAL(VHDL Initiative Towards ASIC Libraries) andmicrowavecircuit design extensions.

In June 2006, the VHDL Technical Committee ofAccellera(delegated by IEEE to work on the next update of the standard) approved so-called Draft 3.0 of VHDL-2006. While maintaining full compatibility with older versions, this proposed standard provides numerous extensions that make writing and managing VHDL code easier. Key changes include incorporation of child standards (1164, 1076.2, 1076.3) into the main 1076 standard, an extended set of operators, more flexible syntax ofcaseandgeneratestatements, incorporation of VHPI (VHDL Procedural Interface) (interface to C/C++ languages) and a subset of PSL (Property Specification Language). These changes should improve quality of synthesizable VHDL code, make testbenches more flexible, and allow wider use of VHDL for system-level descriptions.

In February 2008, Accellera approved VHDL 4.0, also informally known as VHDL 2008, which addressed more than 90 issues discovered during the trial period for version 3.0 and includes enhanced generic types. In 2008, Accellera released VHDL 4.0 to the IEEE for balloting for inclusion in IEEE 1076-2008. The VHDL standard IEEE 1076-2008was published in January 2009.

Standardization

TheIEEEStandard 1076 defines theVHSICHardware Description Language,or VHDL. It was originally developed under contract F33615-83-C-1003 from theUnited States Air Forceawarded in 1983 to a team of Intermetrics, Inc. as language experts and prime contractor,Texas Instrumentsas chip design experts andIBMas computer-system design experts. The language has undergone numerous revisions and has a variety of sub-standards associated with it that augment or extend it in important ways.

1076 was and continues to be a milestone in the design of electronic systems.

Revisions

• IEEE 1076-1987First standardized revision of ver 7.2 of the language from the United States Air Force.
• IEEE 1076-1993(also published withISBN1-55937-376-8). Significant improvements resulting from several years of feedback. Probably the most widely used version with the greatest vendor tool support.
• IEEE 1076-2000.Minor revision. Introduces the use ofprotected types.
• IEEE 1076-2002.Minor revision of 1076-2000. Rules with regard tobuffer portsare relaxed.
  • IEC 61691-1-1:2004.IEC adoption of IEEE 1076-2002.
• IEEE 1076c-2007.Introduced VHPI, the VHDL procedural interface, which provides software with the means to access the VHDL model. The VHDL language required minor modifications to accommodate the VHPI.
• IEEE 1076-2008 (previously referred to as 1076-200x). Major revision released on 2009-01-26. Among other changes, this standard incorporates a basic subset of PSL, allows for generics on packages and subprograms and introduces the use ofexternal names.
  • IEC 61691-1-1:2011.IEC adoption of IEEE 1076-2008.
• IEEE 1076-2019. Major revision.

Related standards

• IEEE 1076.1 VHDL Analog and Mixed-Signal (VHDL-AMS)
• IEEE 1076.1.1 VHDL-AMS Standard Packages (stdpkgs)
• IEEE 1076.2 VHDL Math Package
• IEEE 1076.3 VHDL Synthesis Package (vhdlsynth) (numeric std)
• IEEE 1076.3 VHDL Synthesis Package – Floating Point (fphdl)
• IEEE 1076.4 Timing (VHDL Initiative Towards ASIC Libraries: vital)
• IEEE 1076.6 VHDL Synthesis Interoperability (withdrawn in 2010)
• IEEE 1164VHDL Multivalue Logic (std_logic_1164) Packages

Design

VHDL is generally used to write text models that describe a logic circuit. Such a model is processed by a synthesis program, only if it is part of the logic design. A simulation program is used to test the logic design using simulation models to represent the logic circuits that interface to the design. This collection of simulation models is commonly called atestbench.

A VHDL simulator is typically anevent-driven simulator.This means that each transaction is added to an event queue for a specific scheduled time. E.g. if a signal assignment should occur after 1 nanosecond, the event is added to the queue for time +1ns. Zero delay is also allowed, but still needs to be scheduled: for these casesdelta delayis used, which represent an infinitely small time step. The simulation alters between two modes: statement execution, where triggered statements are evaluated, and event processing, where events in the queue are processed.

VHDL has constructs to handle theparallelisminherent in hardware designs, but these constructs (processes) differ in syntax from the parallel constructs in Ada (tasks). Like Ada, VHDL isstrongly typedand isnot case sensitive.In order to directly represent operations which are common in hardware, there are many features of VHDL which are not found in Ada, such as an extended set of Boolean operators includingnandandnor.

VHDL has file input and output capabilities, and can be used as a general-purpose language for text processing, but files are more commonly used by a simulation testbench for stimulus or verification data. There are some VHDL compilers which build executable binaries. In this case, it might be possible to use VHDL to write atestbenchto verify the functionality of the design using files on the host computer to define stimuli, to interact with the user, and to compare results with those expected. However, most designers leave this job to the simulator.

It is relatively easy for an inexperienced developer to produce code that simulates successfully but that cannot be synthesized into a real device, or is too large to be practical. One particular pitfall is the accidental production oftransparent latchesrather thanD-type flip-flopsas storage elements.

One can design hardware in a VHDL IDE (for FPGA implementation such as Xilinx ISE, Altera Quartus, Synopsys Synplify or Mentor Graphics HDL Designer) to produce theRTLschematic of the desired circuit. After that, the generated schematic can be verified using simulation software which shows the waveforms of inputs and outputs of the circuit after generating the appropriate testbench. To generate an appropriate testbench for a particular circuit or VHDL code, the inputs have to be defined correctly. For example, for clock input, a loop process or an iterative statement is required.

A final point is that when a VHDL model is translated into the "gates and wires" that are mapped onto a programmable logic device such as aCPLDorFPGA,then it is the actual hardware being configured, rather than the VHDL code being "executed" as if on some form of a processor chip.

Advantages

The key advantage of VHDL, when used for systems design, is that it allows the behavior of the required system to be described (modeled) and verified (simulated) before synthesis tools translate the design into real hardware (gates and wires).

Another benefit is that VHDL allows the description of aconcurrent system.VHDL is adataflow languagein which every statement is considered for execution simultaneously, unlike procedural computing languages such as BASIC, C, and assembly code, where a sequence of statements is run sequentially one instruction at a time.

A VHDL project is multipurpose. Being created once, a calculation block can be used in many other projects. However, many formational and functional block parameters can be tuned (capacity parameters, memory size, element base, block composition and interconnection structure).

A VHDL project is portable. Being created for one element base, a computing device project can be ported on another element base, for exampleVLSIwith various technologies.

A big advantage of VHDL compared to originalVerilogis that VHDL has a fulltype system.Designers can use the type system to write much more structured code (especially by declaringrecordtypes).

Design examples

In VHDL, a design consists at a minimum of anentitywhich describes the interface and anarchitecturewhich contains the actual implementation. In addition, most designs import library modules. Some designs also contain multiple architectures andconfigurations.

A simpleAND gatein VHDL would look something like

-- (this is a VHDL comment)
/*
thisisablockcomment(VHDL-2008)
*/
-- import std_logic from the IEEE library
libraryIEEE;
useIEEE.std_logic_1164.all;

-- this is the entity
entityANDGATEis
port(
I1:instd_logic;
I2:instd_logic;
O:outstd_logic);
endentityANDGATE;

-- this is the architecture
architectureRTLofANDGATEis
begin
O<=I1andI2;
endarchitectureRTL;

(Notice thatRTLstands forRegister transfer leveldesign.) While the example above may seem verbose to HDL beginners, many parts are either optional or need to be written only once. Generally simple functions like this are part of a larger behavioral module, instead of having a separate module for something so simple. In addition, use of elements such as thestd_logictype might at first seem to be an overkill. One could easily use the built-inbittype and avoid the library import in the beginning. However, using a form ofmany-valued logic,specifically9-valued logic(U,X,0,1,Z,W,H,L,-), instead of simple bits (0,1) offers a very powerful simulation and debugging tool to the designer which currently does not exist in any other HDL.

In the examples that follow, you will see that VHDL code can be written in a very compact form. However, more experienced designers usually avoid these compact forms and use a more verbose coding style for the sake of readability and maintainability.

Synthesizable constructs and VHDL templates

VHDL is frequently used for two different goals: simulation of electronic designs and synthesis of such designs. Synthesis is a process where a VHDL is compiled and mapped into an implementation technology such as an FPGA or an ASIC.

Not all constructs in VHDL are suitable for synthesis. For example, most constructs that explicitly deal with timing such aswait for 10 ns;are not synthesizable despite being valid for simulation. While different synthesis tools have different capabilities, there exists a commonsynthesizable subsetof VHDL that defines what language constructs and idioms map into common hardware for many synthesis tools. IEEE 1076.6 defines a subset of the language that is considered the official synthesis subset. It is generally considered a "best practice" to write very idiomatic code for synthesis as results can be incorrect or suboptimal for non-standard constructs.

MUX template

Themultiplexer,or 'MUX' as it is usually called, is a simple construct very common in hardware design. The example below demonstrates a simple two to one MUX, with inputsAandB,selectorSand outputX.Note that there are many other ways to express the same MUX in VHDL.

X<=AwhenS='1'elseB;

A more complex example of a MUX with 4x2 inputs and a 2-bit selector:

libraryIEEE;
useIEEE.std_logic_1164.all;
entitymux4is
port(
a1:instd_logic_vector(2downto0);
a2:instd_logic_vector(2downto0);
a3:instd_logic_vector(2downto0);
a4:instd_logic_vector(2downto0);
sel:instd_logic_vector(1downto0);
b:outstd_logic_vector(2downto0)
);
endmux4;
architecturertlofmux4is
-- declarative part: empty
begin
p_mux:process(a1,a2,a3,a4,sel)
begin
caseselis
when"00"=>b<=a1;
when"01"=>b<=a2;
when"10"=>b<=a3;
whenothers=>b<=a4;
endcase;
endprocessp_mux;
endrtl;

Latch template

Atransparent latchis basically one bit of memory which is updated when an enable signal is raised. Again, there are many other ways this can be expressed in VHDL.

-- latch template 1:
Q<=DwhenEnable='1'elseQ;

-- latch template 2:
process(all)
begin
Q<=Dwhen(Enable);
endprocess;

D-type flip-flops

The D-typeflip-flopsamples an incoming signal at the rising (or falling) edge of a clock. This example has an asynchronous, active-high reset, and samples at the rising clock edge.

DFF:process(all)is
begin
ifRSTthen
Q<='0';
elsifrising_edge(CLK)then
Q<=D;
endif;
endprocessDFF;

Another common way to write edge-triggered behavior in VHDL is with the 'event' signal attribute. A single apostrophe has to be written between the signal name and the name of the attribute.

DFF:process(RST,CLK)is
begin
ifRSTthen
Q<='0';
elsifCLK'eventandCLK='1'then
Q<=D;
endif;
endprocessDFF;

VHDL also lends itself to "one-liners" such as

DFF:Q<='0'whenRST='1'elseDwhenrising_edge(clk);

or

DFF:process(all)is
begin
ifrising_edge(CLK)then
Q<=D;
endif;
ifRSTthen
Q<='0';
endif;
endprocessDFF;

or:

LibraryIEEE;
USEIEEE.Std_logic_1164.all;

entityRisingEdge_DFlipFlop_SyncResetis
port(
Q:outstd_logic;
Clk:instd_logic;
sync_reset:instd_logic;
D:instd_logic
);
endRisingEdge_DFlipFlop_SyncReset;

architectureBehavioralofRisingEdge_DFlipFlop_SyncResetis
begin
process(Clk)
begin
if(rising_edge(Clk))then
if(sync_reset='1')then
Q<='0';
else
Q<=D;
endif;
endif;
endprocess;
endBehavioral;

Which can be useful if not all signals (registers) driven by this process should be reset.

Example: a counter

The following example is an up-counter with asynchronous reset, parallel load and configurable width. It demonstrates the use of the 'unsigned' type, type conversions between 'unsigned' and 'std_logic_vector' and VHDLgenerics.The generics are very close to arguments or templates in other traditional programming languages like C++. The example is in VHDL 2008 language.

libraryIEEE;
useIEEE.std_logic_1164.all;
useIEEE.numeric_std.all;-- for the unsigned type

entityCOUNTERis
generic(
WIDTH:innatural:=32);
port(
RST:instd_logic;
CLK:instd_logic;
LOAD:instd_logic;
DATA:instd_logic_vector(WIDTH-1downto0);
Q:bufferstd_logic_vector(WIDTH-1downto0));
endentityCOUNTER;

architectureRTLofCOUNTERis

begin

process(all)is
begin
ifRSTthen
Q<=(others=>'0');
elsifrising_edge(CLK)then
ifLOAD='1'then
Q<=DATA;
else
Q<=std_logic_vector(unsigned(Q)+1);
endif;
endif;
endprocess;

endarchitectureRTL;

More complex counters may add if/then/else statements within therising_edge(CLK) elsifto add other functions, such as count enables, stopping or rolling over at some count value, generating output signals like terminal count signals, etc. Care must be taken with the ordering and nesting of such controls if used together, in order to produce the desired priorities and minimize the number of logic levels needed.

Simulation-only constructs

A large subset of VHDL cannot be translated into hardware. This subset is known as the non-synthesizable or the simulation-only subset of VHDL and can only be used for prototyping, simulation and debugging. For example, the following code will generate a clock with a frequency of 50 MHz. It can, for example, be used to drive a clock input in a design during simulation. It is, however, a simulation-only construct and cannot be implemented in hardware. In actual hardware, the clock is generated externally; it can be scaled down internally by user logic or dedicated hardware.

process
begin
CLK<='1';waitfor10NS;
CLK<='0';waitfor10NS;
endprocess;

The simulation-only constructs can be used to build complex waveforms in very short time. Such waveform can be used, for example, as test vectors for a complex design or as a prototype of some synthesizer logic that will be implemented in the future.

process
begin
waituntilSTART='1';-- wait until START is high

foriin1to10loop-- then wait for a few clock periods...
waituntilrising_edge(CLK);
endloop;

foriin1to10loop-- write numbers 1 to 10 to DATA, 1 every cycle
DATA<=to_unsigned(i,8);
waituntilrising_edge(CLK);
endloop;

-- wait until the output changes
waitonRESULT;

-- now raise ACK for clock period
ACK<='1';
waituntilrising_edge(CLK);
ACK<='0';

-- and so on...
endprocess;

VHDL-2008 Features

Hierarchical Aliases

libraryieee;
useieee.std_logic_1164.all;

entitybfmisendentity;
architecturebehofbfmis
signalen:std_logic;
begin
-- insert implementation here
endarchitecture;

//------------------------------------------
libraryieee;
useieee.std_logic_1164.all;

entitytest1isendentity;
architecturebehoftest1is
begin

ibfm:entitywork.bfm;

-- The testbench process
process
aliasprobe_enis<<signal.test1.ibfm.en:std_logic>>;
begin
probe_en<='1';
waitfor100ns;
probe_en<='0';
waitfor100ns;
probe_en<='1';
waitfor100ns;
std.env.stop(0);
endprocess;

endarchitecture;

Standard libraries

Also referred as standard packages.

IEEE Standard Package

The IEEE Standard Package includes the following:

• numeric_std
• std_logic_1164
  • std_logic_arith
  • std_logic_unsigned
  • std_logic_signed
  • std_logic_misc

VHDL simulators

Main article:List of HDL simulators

Commercial:

• AldecActive-HDL
• CadenceIncisive
• Mentor GraphicsModelSim
• Mentor GraphicsQuesta Advanced Simulator
• SynopsysVCS-MX
• XilinxVivado Design Suite(features the Vivado Simulator)

Other:

• EDA Playground- Free web browser-based VHDL IDE (uses Synopsys VCS, Cadence Incisive, AldecRiviera-PROand GHDL for VHDL simulation)
• GHDLis anopen sourceVHDL compiler that can execute VHDL programs.GHDLonGitHub
• bootby freerangefactory.org is a VHDL compiler and simulator based on GHDL andGTKWave
• VHDL Similiby Symphony EDA is a free commercial VHDL simulator.
• nvcby Nick Gasson is an open source VHDL compiler and simulator
• freehdlby Edwin Naroska was an open source VHDL simulator, abandoned since 2001.

See also

• Altera Hardware Description Language(AHDL)
• Chisel
• Gezel
• numeric std- a standard package which provides arithmetic functions for vectors
• SystemC
• SystemVerilog
• Verilog
• List of HDL simulators

References

Notes

• 1076/INT-1991 – IEEE Standards Interpretations: IEEE Std 1076-1987, IEEE Standard VHDL Language Reference Manual.1992.doi:10.1109/IEEESTD.1992.101084.ISBN0-7381-0987-8.

Further reading

• Peter J. Ashenden, "The Designer's Guide to VHDL, Third Edition (Systems on Silicon)", 2008,ISBN0-1208-8785-1.(The VHDL reference book written by one of the lead developers of the language)
• Bryan Mealy, Fabrizio Tappero (February 2012).[1].The no-frills guide to writing powerful VHDL code for your digital implementations. Archived from the originalFree Range VHDLon 2015-02-13.
• Johan Sandstrom (October 1995)."Comparing Verilog to VHDL Syntactically and Semantically".Integrated System Design.EE Times.— Sandstrom presents a table relating VHDL constructs toVerilogconstructs.
• Qualis Design Corporation (2000-07-20)."VHDL quick reference card"(PDF).1.1. Qualis Design Corporation. Archived fromthe original(PDF)on 2003-12-10.{{cite journal}}:Cite journal requires|journal=(help)
• Qualis Design Corporation (2000-07-20)."1164 packages quick reference card"(PDF).1.0. Qualis Design Corporation. Archived fromthe original(PDF)on 2016-03-14.{{cite journal}}:Cite journal requires|journal=(help)
• Janick Bergeron, "Writing Testbenches: Functional Verification of HDL Models", 2000,ISBN0-7923-7766-4.(The HDL Testbench Bible)

External links

• Official website
• VHDL Analysis and Standardization Group (VASG)