Intel 8086

Intel 8086

A rare Intel C8086 processor in purple ceramic DIP package with side-brazed pins
General information
Launched	1978
Discontinued	1998
Common manufacturer	Intel,AMD,NEC,Fujitsu,Harris(Intersil),OKI,Siemens,Texas Instruments,Mitsubishi,Panasonic(Matsushita)
Performance
Max.CPUclock rate	5 MHz to 10 MHz
Data width	16 bits
Address width	20 bits
Architecture and classification
Technology node	3 μm
Instruction set	x86-16
Physical specifications
Transistors	29,000
Co-processor	Intel 8087,Intel 8089
Package	40 pindual in-line package
Socket	DIP40
Products, models, variants
Variant	8088
History
Predecessor	Intel 8085
Successors	80186and80286(both of which were introduced in early 1982)
Support status
Unsupported

The8086(also callediAPX 86)is a16-bitmicroprocessorchip designed byIntelbetween early 1976 and June 8, 1978, when it was released. TheIntel 8088,released July 1, 1979,is a slightly modified chip with an external 8-bitdata bus(allowing the use of cheaper and fewer supportingICs),and is notable as the processor used in the originalIBM PCdesign.

The 8086 gave rise to thex86architecture, which eventually became Intel's most successful line of processors. On June 5, 2018, Intel released a limited-edition CPU celebrating the 40th anniversary of the Intel 8086, called theIntel Core i7-8086K.

History

Background

In 1972, Intel launched the8008,Intel's first 8-bit microprocessor.It implemented aninstruction setdesigned byDatapoint Corporationwith programmableCRT terminalsin mind, which also proved to be fairly general-purpose. The device needed several additionalICsto produce a functional computer, in part due to it being packaged in a small 18-pin "memory package", which ruled out the use of a separate address bus (Intel was primarily aDRAMmanufacturer at the time).

Two years later, Intel launched the8080,employing the new 40-pinDIL packagesoriginally developed forcalculatorICs to enable a separate address bus. It has an extended instruction set that issource-compatible(notbinary compatible) with the 8008and also includes some16-bitinstructions to make programming easier. The 8080 device was eventually replaced by thedepletion-load-based8085(1977), which sufficed with a single +5 V power supply instead of the three different operating voltages of earlier chips.Other well known 8-bit microprocessors that emerged during these years areMotorola 6800(1974),General Instrument PIC16X(1975),MOS Technology 6502(1975),Zilog Z80(1976), andMotorola 6809(1978).

The first x86 design

Intel 8086 CPU die image

The 8086 project started in May 1976 and was originally intended as a temporary substitute for the ambitious and delayediAPX 432project. It was an attempt to draw attention from the less-delayed 16-bit and32-bitprocessors of other manufacturers —Motorola,Zilog,andNational Semiconductor.

Whereas the 8086 was a 16-bit microprocessor, it used the samemicroarchitectureas Intel's 8-bit microprocessors (8008, 8080, and 8085). This allowedassembly languageprograms written in 8-bit toseamlessly migrate.New instructions and features — such as signed integers, base+offset addressing, and self-repeating operations — were added. Instructions were added to assist source code compilation ofnested functionsin theALGOL-family of languages, includingPascalandPL/M.According to principal architectStephen P. Morse,this was a result of a more software-centric approach. Other enhancements includedmicrocodeinstructions for the multiply and divide assembly language instructions. Designers also anticipatedcoprocessors,such as8087and8089,so the bus structure was designed to be flexible.

The first revision of the instruction set and high level architecture was ready after about three months,and as almost no CAD tools were used, four engineers and 12 layout people were simultaneously working on the chip.The 8086 took a little more than two years from idea to working product, which was considered rather fast for a complex design in the 1970s

The 8086 was sequencedusing a mixture ofrandom logicandmicrocodeand was implemented using depletion-load nMOS circuitry with approximately 20,000 activetransistors(29,000 counting allROMandPLAsites). It was soon moved to a new refined nMOS manufacturing process calledHMOS(for High performance MOS) that Intel originally developed for manufacturing of faststatic RAMproducts.This was followed by HMOS-II, HMOS-III versions, and, eventually, a fully staticCMOSversion for battery powered devices, manufactured using Intel'sCHMOSprocesses.The original chip measured 33 mm² and minimum feature size was 3.2 μm. The MUL and DIV instructions were very slow due to being microcodedso x86 programmers usually just used the bit shift instructions for multiplying and dividing instead.

The 8086 was die-shrunk to 2 μm in 1981; this version also corrected a stack register bug in the original 3.5 μm chips. Later 1.5 μm and CMOS variants were outsourced to other manufacturers and not developed in-house.

The architecture was defined byStephen P. Morsewith some help from Bruce Ravenel (the architect of the 8087) in refining the final revisions. Logic designer Jim McKevitt and John Bayliss were the lead engineers of the hardware-level development teamand Bill Pohlman the manager for the project. The legacy of the 8086 is enduring in the basic instruction set of today's personal computers and servers; the 8086 also lent its last two digits to later extended versions of the design, such as theIntel 286and theIntel 386,all of which eventually became known as thex86family. (Another reference is that thePCI Vendor IDfor Intel devices is 8086_h.)

Details

The 8086 pin assignments in min and max mode

Buses and operation

All internal registers, as well as internal and external data buses, are 16 bits wide, which firmly established the "16-bit microprocessor" identity of the 8086. A 20-bit external address bus provides a 1MiBphysical address space (2²⁰= 1,048,576 x 1byte). This address space is addressed by means of internal memory "segmentation". The data bus ismultiplexedwith the address bus in order to fit all of the control lines into a standard 40-pindual in-line package.It provides a 16-bit I/O address bus, supporting 64KBof separate I/O space. The maximum linear address space is limited to 64 KB, simply because internal address/index registers are only 16 bits wide. Programming over 64 KB memory boundaries involves adjusting the segment registers (see below); this difficulty existed until the80386architecture introduced wider (32-bit) registers (the memory management hardware in the80286did not help in this regard, as its registers are still only 16 bits wide).

Hardware modes of 8086

Some of the control pins, which carry essential signals for all external operations, have more than one function depending upon whether the device is operated inminormaxmode. The former mode is intended for small single-processor systems, while the latter is for medium or large systems using more than one processor (a kind of multiprocessor mode). Maximum mode is required when using an 8087 or 8089 coprocessor. The voltage on pin 33 (MN/MX) determines the mode. Changing the state of pin 33 changes the function of certain other pins, most of which have to do with how the CPU handles the (local) bus.The mode is usually hardwired into the circuit and therefore cannot be changed by software. The workings of these modes are described in terms of timing diagrams in Intel datasheets and manuals. In minimum mode, all control signals are generated by the 8086 itself.

Registers and instruction

Intel 8086 registers

19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 (bit position) Main registers AH AL AX(primary accumulator) 0 0 0 0 BH BL BX(base, accumulator) CH CL CX(counter, accumulator) DH DL DX(accumulator, extended acc) Index registers 0 0 0 0 SI SourceIndex 0 0 0 0 DI DestinationIndex 0 0 0 0 BP BasePointer 0 0 0 0 SP StackPointer Program counter 0 0 0 0 IP InstructionPointer Segment registers CS 0 0 0 0 CodeSegment DS 0 0 0 0 DataSegment ES 0 0 0 0 ExtraSegment SS 0 0 0 0 StackSegment Status register - - - - O D I T S Z - A - P - C Flags

The 8086 has eight more-or-less general 16-bitregisters(including thestack pointerbut excluding the instruction pointer, flag register and segment registers). Four of them, AX, BX, CX, DX, can also be accessed as 8-bit register pairs (see figure) while the other four, SI, DI, BP, SP, are 16-bit only.

Due to a compact encoding inspired by 8-bit processors, most instructions are one-address or two-address operations, which means that the result is stored in one of the operands. At most one of the operands can be in memory, but this memory operand can also be thedestination,while the other operand, thesource,can be eitherregisterorimmediate.A single memory location can also often be used as bothsourceanddestinationwhich, among other factors, further contributes to acode densitycomparable to (and often better than) most eight-bit machines at the time.

The degree of generality of most registers is much greater than in the 8080 or 8085. However, 8086 registers were more specialized than in most contemporaryminicomputersand are also used implicitly by some instructions. While perfectly sensible for the assembly programmer, this makes register allocation for compilers more complicated compared to more orthogonal 16-bit and 32-bit processors of the time such as thePDP-11,VAX,68000,32016,etc. On the other hand, being more regular than the rather minimalistic but ubiquitous 8-bit microprocessors such as the6502,6800,6809,8085,MCS-48,8051,and other contemporary accumulator-based machines, it is significantly easier to construct an efficientcode generatorfor the 8086 architecture.

Another factor for this is that the 8086 also introduced some new instructions (not present in the 8080 and 8085) to better support stack-based high-level programming languages such as Pascal andPL/M;some of the more useful instructions arepushmem-op,andretsize,supporting the "Pascalcalling convention"directly. (Several others, such aspushimmedandenter,were added in the subsequent 80186, 80286, and 80386 processors.)

A 64 KB (one segment)stackgrowing towards lower addresses is supported inhardware;16-bit words are pushed onto the stack, and the top of the stack is pointed to by SS:SP. There are 256interrupts,which can be invoked by both hardware and software. The interrupts can cascade, using the stack to store thereturn addresses.

The 8086 has 64 K of 8-bit (or alternatively 32 K of 16-bit word)I/O portspace.

Flags

The 8086 has a 16-bitflags register.Nine of these condition code flags are active, and indicate the current state of the processor:Carry flag(CF),Parity flag(PF),Auxiliary carry flag(AF),Zero flag(ZF),Sign flag(SF),Trap flag(TF),Interrupt flag(IF),Direction flag(DF), andOverflow flag(OF). Also referred to as the status word, the layout of the flags register is as follows:

Bit	15-12	11	10	9	8	7	6	5	4	3	2	1	0
Flag		OF	DF	IF	TF	SF	ZF		AF		PF		CF

Segmentation

See also:x86 memory segmentation

There are also four 16-bitsegmentregisters (see figure) that allow the 8086CPUto access onemegabyteof memory in an unusual way. Rather than concatenating the segment register with the address register, as in most processors whose address space exceeds their register size, the 8086 shifts the 16-bit segment only four bits left before adding it to the 16-bit offset (16×segment + offset), therefore producing a 20-bit external (or effective or physical) address from the 32-bit segment:offset pair. As a result, each external address can be referred to by 2¹²= 4096 different segment:offset pairs.

0110 1000 1000 01110000	Segment,	16 bits, shifted 4 bits left (or multiplied by 0x10)
+1011 0100 1010 1001	Offset,	16 bits
0111 0011 1101 0001 1001	Address,	20 bits

Although considered complicated and cumbersome by many programmers, this scheme also has advantages; a small program (less than 64 KB) can be loaded starting at a fixed offset (such as 0000) in its own segment, avoiding the need forrelocation,with at most 15 bytes of alignment waste.

Compilers for the 8086 family commonly support two types ofpointer,nearandfar.Near pointers are 16-bit offsets implicitly associated with the program's code or data segment and so can be used only within parts of a program small enough to fit in one segment. Far pointers are 32-bit segment:offset pairs resolving to 20-bit external addresses. Some compilers also supporthugepointers, which are like far pointers except thatpointer arithmeticon a huge pointer treats it as a linear 20-bit pointer, while pointer arithmetic on a far pointerwraps aroundwithin its 16-bit offset without touching the segment part of the address.

To avoid the need to specifynearandfaron numerous pointers, data structures, and functions, compilers also support "memory models" which specify default pointer sizes. Thetiny(max 64K),small(max 128K),compact(data > 64K),medium(code > 64K),large(code,data > 64K), andhuge(individual arrays > 64K) models cover practical combinations of near, far, and huge pointers for code and data. Thetinymodel means that code and data are shared in a single segment, just as in most 8-bit based processors, and can be used to build.comfiles for instance. Precompiled libraries often come in several versions compiled for different memory models.

According to Morse et al.,.the designers actually contemplated using an 8-bit shift (instead of 4-bit), in order to create a 16 MB physical address space. However, as this would have forced segments to begin on 256-byte boundaries, and 1 MB was considered very large for a microprocessor around 1976, the idea was dismissed. Also, there were not enough pins available on a low cost 40-pin package for the additional four address bus pins.

In principle, the address space of the x86 seriescouldhave been extended in later processors by increasing the shift value, as long as applications obtained their segments from the operating system and did not make assumptions about the equivalence of different segment:offset pairs.In practice the use of "huge" pointers and similar mechanisms was widespread and the flat 32-bit addressing made possible with the 32-bit offset registers in the 80386 eventually extended the limited addressing range in a more general way.

The instruction stream is fetched from memory as words and is addressed internally by the processor to the byte level as necessary. An instruction stream queuing mechanism allows up to 6 bytes of the instruction stream to be queued while waiting for decoding and execution. The queue acts as a First-In-First-Out (FIFO) buffer, from which the Execution Unit (EU) extracts instruction bytes as required. Whenever there is space for at least two bytes in the queue, the BIU will attempt a word fetch memory cycle. If the queue is empty (following a branch instruction, for example), the first byte into the queue immediately becomes available to the EU.

Porting older software

Small programs could ignore the segmentation and just use plain 16-bit addressing. This allows8-bitsoftware to be quite easily ported to the 8086. The authors of mostDOSimplementations took advantage of this by providing anApplication Programming Interfacevery similar toCP/Mas well as including the simple.comexecutable file format, identical to CP/M. This was important when the 8086 and MS-DOS were new, because it allowed many existing CP/M (and other) applications to be quickly made available, greatly easing acceptance of the new platform.

Example code

The following 8086assemblysource code is for a subroutine named_strtolowerthat copies a null-terminatedASCIIZcharacter string from one location to another, converting all alphabetic characters to lower case. The string is copied one byte (8-bit character) at a time.

0000 0000 55 0001 89 E5 0003 56 0004 57 0005 8B 75 06 0008 8B 7D 04 000B FC 000C AC 000D 3C 41 000F 7C 06 0011 3C 5A 0013 7F 02 0015 04 20 0017 AA 0018 08 C0 001A 75 F0 001C 5F 001D 5E 001E 5D 001F C3 001F

;_strtolower: ;Copy a null-terminated ASCII string, converting ;all alphabetic characters to lower case. ;ES=DS ;Entry stack parameters ;[SP+4] = src, Address of source string ;[SP+2] = dst, Address of target string ;[SP+0] = Return address ; _strtolowerproc pushbp;Set up the call frame movbp,sp pushsi pushdi movsi,[bp+6];Set SI = src (+2 due to push bp) movdi,[bp+4];Set DI = dst cld;string direction ascending loop:lodsb;Load AL from [si], inc si cmpal,'A';If AL < 'A', jlcopy;Skip conversion cmpal,'Z';If AL > 'Z', jgcopy;Skip conversion addal,'a'-'A';Convert AL to lowercase copy:stosb;Store AL to [di], inc di oral,al;If AL <> 0, jneloop;Repeat the loop done:popdi;restore di and si popsi popbp;Restore the prev call frame ret;Return to caller endproc

The example code uses the BP (base pointer) register to establish acall frame,an area on the stack that contains all of the parameters and local variables for the execution of the subroutine. This kind ofcalling conventionsupportsreentrantandrecursivecode and has been used by Algol-like languages since the late 1950s. A flat memory model is assumed, specifically, that the DS and ES segments address the same region of memory.

Performance

Simplified block diagram over Intel 8088 (a variant of 8086); 1=main & index registers; 2=segment registers and IP; 3=address adder; 4=internal address bus; 5=instruction queue; 6=control unit (very simplified!); 7=bus interface; 8=internal databus; 9=ALU; 10/11/12=external address/data/control bus.

Although partly shadowed by other design choices in this particular chip, themultiplexedaddress anddata buseslimit performance slightly; transfers of 16-bit or 8-bit quantities are done in a four-clock memory access cycle, which is faster on 16-bit, although slower on 8-bit quantities, compared to many contemporary 8-bit based CPUs. As instructions vary from one to six bytes, fetch and execution are madeconcurrentand decoupled into separate units (as it remains in today's x86 processors): Thebus interface unitfeeds the instruction stream to theexecution unitthrough a 6-byte prefetch queue (a form of loosely coupledpipelining), speeding up operations onregistersandimmediates,while memory operations became slower (four years later, this performance problem was fixed with the80186and80286). However, the full (instead of partial) 16-bit architecture with a full widthALUmeant that 16-bit arithmetic instructions could now be performed with a single ALU cycle (instead of two, via internal carry, as in the 8080 and 8085), speeding up such instructions considerably. Combined withorthogonalizationsof operations versusoperandtypes andaddressing modes,as well as other enhancements, this made the performance gain over the 8080 or 8085 fairly significant, despite cases where the older chips may be faster (see below).

Execution times for typical instructions (in clock cycles)

instruction	register-register	register immediate	register-memory	memory-register	memory-immediate
mov	2	4	8+EA	9+EA	10+EA
ALU	3	4	9+EA,	16+EA,	17+EA
jump	register≥ 11;label≥ 15;condition,label≥ 16
integer multiply	70~160 (depending on operanddataas well as size)includingany EA
integer divide	80~190 (depending on operanddataas well as size)includingany EA

• EA = time to compute effective address, ranging from 5 to 12 cycles.
• Timings are best case, depending on prefetch status, instruction alignment, and other factors.

As can be seen from these tables, operations on registers and immediates were fast (between 2 and 4 cycles), while memory-operand instructions and jumps were quite slow; jumps took more cycles than on the simple8080and8085,and the 8088 (used in the IBM PC) was additionally hampered by its narrower bus. The reasons why most memory related instructions were slow were threefold:

• Loosely coupled fetch and execution units are efficient for instruction prefetch, but not for jumps and random data access (without special measures).
• No dedicated address calculation adder was afforded; the microcode routines had to use the main ALU for this (although there was a dedicatedsegment+offsetadder).
• The address and data buses weremultiplexed,forcing a slightly longer (33~50%) bus cycle than in typical contemporary 8-bit processors.

However, memory access performance was drastically enhanced with Intel's next generation of 8086 family CPUs. The80186and80286both had dedicated address calculation hardware, saving many cycles, and the 80286 also had separate (non-multiplexed) address and data buses.

Floating point

The 8086/8088 could be connected to a mathematical coprocessor to add hardware/microcode-basedfloating-pointperformance. TheIntel 8087was the standard math coprocessor for the 8086 and 8088, operating on 80-bit numbers. Manufacturers likeCyrix(8087-compatible) andWeitek(not8087-compatible) eventually came up with high-performance floating-point coprocessors that competed with the 8087.

Chip versions

The clock frequency was originally limited to 5 MHz,but the last versions inHMOSwere specified for 10 MHz. HMOS-III andCMOSversions were manufactured for a long time (at least a while into the 1990s) forembedded systems,although its successor, the80186/80188(which includes some on-chip peripherals), has been more popular for embedded use.

The 80C86, the CMOS version of the 8086, was used in theGRiDPad,Toshiba T1200,HP 110,and finally the 1998–1999Lunar Prospector.

For the packaging, the Intel 8086 was available both in ceramic and plastic DIP packages.

• 
  A ceramic D8086 variant
• 
  A plastic P8086 variant

List of Intel 8086

Model number	Frequency	Technology	Temperature range	Package	Date of release	Price (USD)
8086	5 MHz	HMOS	0 °C to 70 °C		June 8, 1978	$86.65
8086-1	10 MHz	HMOS II	Commercial
8086-2	8 MHz	HMOS II	Commercial		January/February 1980	$200
8086-4	4 MHz	HMOS	Commercial			$72.50
I8086	5 MHz	HMOS	Industrial −40 °C to +85 °C		May/June 1980	$173.25
M8086	5 MHz	HMOS	Military grade −55 °C to +125 °C
80C86		CMOS		44 PinPLCC

Derivatives and clones

Compatible—and, in many cases, enhanced—versions were manufactured byFujitsu,Harris/Intersil,OKI,Siemens,Texas Instruments,NEC,Mitsubishi,andAMD.For example, theNEC V20andNEC V30pair were hardware-compatible with the 8088 and 8086 even though NEC made original Intel clones μPD8088D and μPD8086D respectively, but incorporated the instruction set of the 80186 along with some (but not all) of the 80186 speed enhancements, providing a drop-in capability to upgrade both instruction set and processing speed without manufacturers having to modify their designs. Such relatively simple and low-power 8086-compatible processors in CMOS are still used in embedded systems.

The electronics industry of theSoviet Unionwas able to replicate the 8086 throughbothindustrial espionageand reverse engineering.The resulting chip,K1810VM86,was binary and pin-compatible with the 8086.

i8086 and i8088 were respectively the cores of the Soviet-made PC-compatibleEC1831andEC1832desktops. (EC1831 is the EC identification of IZOT 1036C and EC1832 is the EC identification of IZOT 1037C, developed and manufactured in Bulgaria. EC stands for Единая Система.) However, the EC1831 computer (IZOT 1036C) had significant hardware differences from the IBM PC prototype. The EC1831 was the first PC-compatible computer with dynamic bus sizing (US Pat. No 4,831,514). Later some of the EC1831 principles were adopted in PS/2 (US Pat. No 5,548,786) and some other machines (UK Patent Application, Publication No. GB-A-2211325, Published June 28, 1989).

• 
  Soviet cloneK1810VM86
• 
  OKIM80C86AQFP-56
• 
  NEC μPD8086D-2 (8 MHz) from the year 1984, week 19 JAPAN (clone of Intel D8086-2)
• 
  TheAMDD8086

Support chips

• Intel 8237:direct memory access (DMA) controller
• Intel 8251:universal synchronous/asynchronous receiver/transmitter at 19.2 kbit/s
• Intel 8253:programmable interval timer, 3x 16-bit max 10 MHz
• Intel 8255:programmable peripheral interface, 3x 8-bit I/O pins used for printer connection etc.
• Intel 8259:programmable interrupt controller
• Intel 8279:keyboard/display controller, scans a keyboard matrix and display matrix like7-seg
• Intel 8282/8283:8-bit latch
• Intel 8284:clock generator
• Intel 8286/8287:bidirectional 8-bit driver. In 1980 both Intel I8286/I8287 (industrial grade) version were available for US$16.25 in quantities of 100.
• Intel 8288:bus controller
• Intel 8289:bus arbiter
• NEC μPD765 or Intel 8272A:floppy controller

Microcomputers using the 8086

• The IntelMultibus-compatiblesingle-board computerISBC 86/12 was announced in 1978.
• TheXerox NoteTakerwas one of the earliestportable computerdesigns in 1978 and used three 8086 chips (as CPU, graphics processor, and I/O processor), but never entered commercial production.
• Seattle Computer ProductsshippedS-100 busbased 8086 systems (SCP200B) as early as November 1979.
• The NorwegianMycron2000, introduced in 1980.
• One of the most influential microcomputers of all, theIBM PC,used theIntel 8088,a version of the 8086 with an 8-bitdata bus(as mentioned above).
• The firstCompaq Deskproused an 8086 running at 7.16 MHz, but was compatible with add-in cards designed for the 4.77 MHzIBM PC XTand could switch the CPU down to the lower speed (which also switched in a memory bus buffer to simulate the 8088's slower access) to avoid software timing issues.
• An 8 MHz 8086-2 was used in theAT&T 6300 PC(built byOlivetti,and known globally under several brands and model numbers), an IBM PC-compatible desktop microcomputer. The M24 / PC 6300 has IBM PC/XT compatible 8-bit expansion slots, but some of them have a proprietary extension providing the full 16-bit data bus of the 8086 CPU (similar in concept to the 16-bit slots of theIBM PC AT,but different in the design details, and physically incompatible), and all system peripherals including the onboard video system also enjoy 16-bit data transfers. The later Olivetti M24SP featured an 8086-2 running at the full maximum 10 MHz.
• TheIBM PS/2models25and30were built with an 8 MHz 8086.
• TheAmstrad PC1512,PC1640,PC2086, PC3086 and PC5086 all used 8086 CPUs at 8 MHz.
• TheNEC PC-9801.
• TheTandy 1000SL-series and RL machines used 9.47 MHz 8086 CPUs.
• TheIBM Displaywriterword processing machineand the Wang Professional Computer, manufactured byWang Laboratories,also used the 8086.
• NASAused original 8086 CPUs on equipment for ground-based maintenance of theSpace Shuttle Discoveryuntil the end of the space shuttle program in 2011. This decision was made to preventsoftware regressionthat might result from upgrading or from switching to imperfect clones.
• KAMAN Process and Area Radiation Monitors
• TheTektronix4170 ranCP/M-86and used an 80864170 Local Graphics Processing Unit Instruction Manual(PDF)

See also

• Transistor count
• iAPX,for the iAPX name

External links

• Intel datasheets
• List of 8086 CPUs and their clones at CPUworld.com
• 8086 Pinouts
• Maximum Mode InterfaceArchivedfrom the original on July 21, 2011. Retrieved July 10, 2022.
• The 8086 User's manual October 1979 INTEL Corporation(PDFdocument)
• 8086 program codes using emu8086 (Version 4.08) Emulator
• Jenner, Andrew (September 2020)."8086 microcode disassembled".Reenigne blog.
• Shirriff, Ken (June 2020)."A look at the die of the 8086 processor".
  • — (June 2020)."Die shrink: How Intel scaled down the 8086 processor".
  • — (July 2020)."The Intel 8086 processor's registers: from chip to transistors".
  • — (August 2020)."Reverse-engineering the adder inside the Intel 8086".
  • — (August 2020)."Reverse-engineering the 8086's Arithmetic/Logic Unit from die photos".
  • — (November 2022)."The unusual bootstrap drivers inside the 8086 microprocessor chip".
  • — (November 2022)."A bug fix in the 8086 microprocessor, revealed in the die's silicon".
  • — (December 2022)."How the 8086 processor's microcode engine works".
  • — (January 2023)."Inside the 8086 processor's instruction prefetch circuitry".
  • — (January 2023)."The 8086 processor's microcode pipeline from die analysis".
  • — (January 2023)."Counting the transistors in the 8086 processor: it's harder than you might think".
  • — (January 2023)."Reverse-engineering the conditional jump circuitry in the 8086 processor".
  • — (January 2023)."Reverse-engineering the Intel 8086 processor's HALT circuits".
  • — (January 2023)."Understanding the x86's Decimal Adjust after Addition (DAA) instruction".
  • — (February 2023)."Silicon reverse-engineering: the Intel 8086 processor's flag circuitry".
  • — (February 2023)."Reverse-engineering the interrupt circuitry in the Intel 8086 processor".
  • — (February 2023)."Reverse-engineering the ModR/M addressing microcode in the Intel 8086 processor".
  • — (March 2023)."How the 8086 processor determines the length of an instruction".
  • — (March 2023)."Reverse-engineering the multiplication algorithm in the Intel 8086 processor".
  • — (March 2023)."Reverse-engineering the register codes for the 8086 processor's microcode".
  • — (April 2023)."The microcode and hardware in the 8086 processor that perform string operations".
  • — (April 2023)."Reverse-engineering the division microcode in the Intel 8086 processor".
  • — (May 2023)."The Group Decode ROM: The 8086 processor's first step of instruction decoding".
  • — (July 2023)."Reverse-engineering the 8086 processor's address and data pin circuits".
  • — (July 2023)."Undocumented 8086 instructions, explained by the microcode".
  • — (August 2023)."Tracing the roots of the 8086 instruction set to the Datapoint 2200 minicomputer".
  • — (August 2023)."A close look at the 8086 processor's bus hold circuitry".
  • — (October 2023)."How flip-flops are implemented in the Intel 8086 processor".
  • — (March 2024)."The Intel 8088 processor's instruction prefetch circuitry: a look inside".
  • — (April 2024)."Talking to memory: Inside the Intel 8088 processor's bus interface state machine".