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DDR4 SDRAM

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This article is about DDR4 SDRAM. For graphics DDR4, seeGDDR4 SDRAM.For the video game, seeDance Dance Revolution 4thMix.
DDR4 SDRAM
Double Data Rate 4 Synchronous Dynamic Random-Access Memory
Type ofRAM
16GiB[1]DDR4-2666 1.2 VUDIMM
DeveloperJEDEC
TypeSynchronous dynamic random-access memory(SDRAM)
Generation4th generation
Release date2014;10 years ago(2014)
Standards
  • DDR4-1600 (PC4-12800)
  • DDR4-1866 (PC4-14900)
  • DDR4-2133 (PC4-17000)
  • DDR4-2400 (PC4-19200)
  • DDR4-2666 (PC4-21333)
  • DDR4-2933 (PC4-23466)
  • DDR4-3200 (PC4-25600)
Clock rate800–1600 MHz
Cycle time0.625 ns to 1.25 ns
Prefetch buffer8n-prefetch architecture
Busclock rate1600 MT/s to 3200 MT/s.
Transfer rate12.8 GB/s to 25.6 GB/s
VoltageReference 1.2 V
PredecessorDDR3 SDRAM(2007)
SuccessorDDR5 SDRAM(2020)

Double Data Rate 4 Synchronous Dynamic Random-Access Memory(DDR4 SDRAM) is a type ofsynchronous dynamic random-access memorywith a highbandwidth( "double data rate") interface.

Released to the market in 2014,[2][3][4]it is a variant ofdynamic random-access memory(DRAM), some of which have been in use since the early 1970s,[5]and a higher-speed successor to theDDR2andDDR3technologies.

DDR4 is not compatible with any earlier type of random-access memory (RAM) due to different signaling voltage and physical interface, besides other factors.

DDR4SDRAMwas released to the public market in Q2 2014, focusing onECC memory,[6]while the non-ECC DDR4 modules became available in Q3 2014, accompanying the launch ofHaswell-Eprocessors that require DDR4 memory.[7]

Features

[edit]

The primary advantages of DDR4 over its predecessor, DDR3, include higher module density and lower voltage requirements, coupled with higherdata rate transferspeeds. The DDR4 standard allows forDIMMsof up to 64GBin capacity, compared to DDR3's maximum of 16 GB per DIMM.[1][8][failed verification]

Unlike previous generations of DDR memory,prefetchhasnotbeen increased above the 8n used in DDR3;[9]: 16 the basic burst size is eight 64-bit words, and higher bandwidths are achieved by sending more read/write commands per second. To allow this, the standard divides the DRAM banks into two or four selectable bank groups,[10]where transfers to different bank groups may be done more rapidly.

Because power consumption increases with speed, the reduced voltage allows higher speed operation without unreasonable power and cooling requirements.

DDR4 RAMoperates at a voltage of1.2 Vand supports frequencies between800 and 1600 MHz(DDR4-1600 through DDR4-3200). Compared to DDR3, which operates at1.5 Vwithfrequenciesfrom400 to 1067 MHz(DDR3-800 through DDR3-2133), DDR4 offers better performance andenergy efficiency.DDR4 speeds are advertised as double the base clock rate due to its Double Data Rate (DDR) nature, with common speeds including DDR4-2400 and DDR4-3200, and higher speeds like DDR4-4266 and DDR4-5000 available at a premium. Unlike DDR3, DDR4 does not have a low voltage variant; it consistently operates at1.2 V.Additionally, DDR4 improves on DDR3 with a longer burst length of 16 and supports larger memory capacities, enhancing both performance and system flexibility.[11][12]

Timeline

[edit]
The first DDR4 memory module prototype was manufactured bySamsungand announced in January 2011.[a]
Physical comparison ofDDR,DDR2,DDR3,and DDR4 SDRAM
Front and back of 8 GB[1]DDR4 memory modules
  • 2005:Standards bodyJEDECbegan working on a successor to DDR3 around 2005,[14]about 2 years before the launch of DDR3 in 2007.[15][16]The high-level architecture of DDR4 was planned for completion in 2008.[17]
  • 2007:Some advance information was published in 2007,[18]and a guest speaker fromQimondaprovided further public details in a presentation at the August 2008San FranciscoIntel Developer Forum(IDF).[18][19][20][21]DDR4 was described as involving a 30 nm process at 1.2 volts, withbusfrequencies of 2133MT/s"regular" speed and 3200 MT/s "enthusiast" speed, and reaching market in 2012, before transitioning to 1 volt in 2013.[19][21]
  • 2009:In February,Samsungvalidated 40 nm DRAM chips, considered a "significant step" towards DDR4 development[22]since in 2009, DRAM chips were only beginning to migrate to a 50 nm process.[23]
  • 2010:Subsequently, further details were revealed at MemCon 2010,Tokyo(a computer memory industry event), at which a presentation by a JEDEC director titled "Time to rethink DDR4"[24]with a slide titled "New roadmap: More realistic roadmap is 2015" led some websites to report that the introduction of DDR4 was probably[25]or definitely[26][27]delayed until 2015. However, DDR4test sampleswere announced in line with the original schedule in early 2011 at which time manufacturers began to advise that large scale commercial production and release to market was scheduled for 2012.[2]
  • 2011:In January,Samsungannounced the completion and release for testing of a 2 GB[1]DDR4DRAM module based on a process between 30 and 39nm.[28]It has a maximum data transfer rate of 2133MT/sat 1.2 V, usespseudo open draintechnology (adapted fromgraphics DDRmemory[29]) and draws 40% less power than an equivalent DDR3 module.[28][30]
    In April,Hynixannounced the production of 2 GB[1]DDR4 modules at 2400 MT/s, also running at 1.2 V on a process between 30 and 39 nm (exact process unspecified),[2]adding that it anticipated commencing high volume production in the second half of 2012.[2]Semiconductor processes for DDR4 were expected to transition to sub-30 nm at some point between late 2012 and 2014.[31][32]
  • 2012:In May,Micronannounced[3]it was aiming at starting production in late 2012 of 30 nm modules. In July, Samsung announced that it would begin sampling the industry's first 16 GB[1]registered dual inline memory modules (RDIMMs) using DDR4 SDRAM for enterprise server systems.[33][34]In September, JEDEC released the final specification of DDR4.[35]
  • 2013:DDR4 was expected to represent 5% of the DRAM market in 2013,[2]and to reachmass marketadoption and 50%market penetrationaround 2015;[2]as of 2013, however, adoption of DDR4 had been delayed and it was no longer expected to reach a majority of the market until 2016 or later.[36]The transition from DDR3 to DDR4 is thus taking longer than the approximately five years taken for DDR3 to achieve mass market transition over DDR2.[31]In part, this is because changes required to other components would affect all other parts of computer systems, which would need to be updated to work with DDR4.[37]
  • 2014:In April, Hynix announced that it had developed the world's first highest-density 128 GB module based on 8GbitDDR4 using 20 nm technology. The module works at 2133 MHz, with a 64-bit I/O, and processes up to 17 GB of data per second.
  • 2016:In April, Samsung announced that they had begun to mass-produce DRAM on a "10 nm-class" process, by which they mean the 1x nm node regime of 16 nm to 19 nm, which supports a 30% faster data transfer rate of 3,200 Mbit/s.[38]Previously, a size of 20 nm was used.[39][40]
  • 2020:DDR5 RAM was formally introduced by theJEDECSolid State Technology Association in July 2020 as the successor to DDR4. JEDEC, a global leader in developing open standards for themicroelectronicsindustry, spearheaded the development of DDR5 to address the growing demands for higher performance and efficiency in modern computing. TheDDR5standard builds on the advancements of DDR4 with notable improvements in bandwidth, efficiency, and capacity, offering a base data rate of 4800 MT/s and supporting higher speeds as the technology matures. DDR5 also features enhanced power management, increased burst length, and improved prefetch capabilities, making it suitable for a wide range of applications from high-performance gaming to data-intensive computing tasks.

Market perception and adoption

[edit]

In April 2013, a news writer atInternational Data Group(IDG) – an American technology research business originally part ofIDC– produced an analysis of their perceptions related to DDR4 SDRAM.[41]The conclusions were that the increasing popularity ofmobile computingand other devices using slower but low-powered memory, the slowing of growth in the traditionaldesktop computingsector, and theconsolidationof the memory manufacturing marketplace, meant that margins on RAM were tight.

As a result, the desiredpremium pricingfor the new technology was harder to achieve, and capacity had shifted to other sectors. SDRAM manufacturers and chipset creators were, to an extent, "stuck between a rock and a hard place" where "nobody wants to pay a premium for DDR4 products, and manufacturers don't want to make the memory if they are not going to get a premium", according to Mike Howard from iSuppli.[41]A switch inconsumer sentimenttoward desktop computing and release of processors having DDR4 support byIntelandAMDcould therefore potentially lead to "aggressive" growth.[41]

Intel's 2014Haswellroadmap, revealed the company's first use of DDR4 SDRAM inHaswell-EPprocessors.[42]

AMD'sRyzenprocessors, revealed in 2016 and shipped in 2017, use DDR4 SDRAM.[43]

Operation

[edit]

DDR4 RAMoperates with a primary supply voltage of1.2 Vand an auxiliary2.5 Vsupply for wordline boosting (VPP). This contrasts withDDR3,which runs at1.5 Vand had lower voltage variants at1.35 Vintroduced in 2013. DDR4 was introduced with a minimum transfer rate of2133 MT/s,influenced by DDR3's nearing limit at similar speeds, and is expected to reach up to4266 MT/s.Notable improvements in DDR4 include increased data transfer rates and enhanced efficiency. Early DDR4 samples, such as those fromSamsungin January 2011, showed a CAS latency of13clock cycles,comparable to the DDR2 to DDR3 transition. Additionally, DDR4 features a longer burst length of 16, higher capacity support, and improvedsignal integritywith tighter pin spacing (0.85 mm vs. 1.0 mm), slightly increased height (31.25 mm vs. 30.35 mm), and increased thickness (1.2 mm vs. 1.0 mm) for better signal routing and performance.

Internal banks are increased to 16 (4 bank select bits), with up to 8 ranks per DIMM.[9]: 16 

Protocol changes include:[9]: 20 

  • Parity on the command/address bus
  • Data bus inversion (likeGDDR4)
  • CRCon the data bus
  • Independent programming of individual DRAMs on a DIMM, to allow better control ofon-die termination.

Increased memory density is anticipated, possibly using TSV ( "through-silicon via") or other3D stacking processes.[31][37][44][45]The DDR4 specification will include standardized3D stacking"from the start" according to JEDEC,[45]with provision for up to8 stackeddies.[9]: 12 X-bit Labs predicted that "as a result DDR4 memory chips with very high density will become relatively inexpensive".[37]

Switched memory banks are also an anticipated option for servers.[31][44]

In 2008, the bookWafer Level 3-D ICs Process Technologyhighlighted concerns about the increasing die area consumption due to non-scaling analog elements likecharge pumps,voltage regulators,and additional circuitry. These components, includingCRCerror-detection,on-die termination,burst hardware, programmable pipelines, low impedance, and a greater need forsense amplifiers(driven by reduced bits per bitline due to lower voltage), have significantly increased bandwidth but at the cost of occupying more die area. Consequently, the proportion of die allocated to the memory array itself has decreased over time: from70–78%for SDRAM and DDR1 to47%for DDR2,38%for DDR3, and potentially less than30%for DDR4.[46]

The specification defined standards for ×4, ×8 and ×16 memory devices with capacities of 2, 4, 8 and 16 Gbit.[1][47]

In addition to bandwidth and capacity variants, DDR4 modules can optionally implement:

  • ECC,which is an extra data byte lane used for correcting minor errors and detecting major errors for better reliability. Modules with ECC are identified by an additional ECC in their designation. PC4-19200 ECC or PC4-19200E is a PC4-19200 module with ECC.[48]
  • Registered (or buffered) RAMenhances signal integrity, which can improve clock rates and allow for higher physical slot capacity, by buffering signals electrically. This comes at the cost of an additional clock cycle of latency. These modules are identified by an "R" in their designation, such asPC4-19200R.Typically, modules with this designation are also ECC (Error-Correcting Code) Registered, though the 'E' for ECC may not always be included in the designation. Conversely, non-registered RAM, also known as unbuffered RAM, is identified by a "U" in the designation. e.g. PC4-19200U.[48]
  • Be Load reduced modules,which are designated by LR and are similar to registered/buffered memory, in a way thatLRDIMMmodules buffer both control and data lines while retaining the parallel nature of all signals. As such, LRDIMM memory provides larger overall maximum memory capacities, while addressing some of the performance and power consumption issues of FB memory induced by the required conversion between serial and parallel signal forms.[48]

Command encoding

[edit]
DDR4 command encoding[49]
Command CS
 BG1–0,
BA1–0		 ACT
 A17
 A16
RAS		 A15
CAS		 A14
WE		 A13
 A12
BC		 A11
 A10
AP		 A9–0
Deselect (no operation) H X
Active (activate): open a row L Bank L Row address
No operation L V H V H H H V
ZQ calibration L V H V H H L V Long V
Read (BC, burst chop) L Bank H V H L H V BC V AP Column
Write (AP, auto-precharge) L Bank H V H L L V BC V AP Column
Unassigned, reserved L V v V L H H V
Precharge all banks L V H V L H L V H V
Precharge one bank L Bank H V L H L V L V
Refresh L V H V L L H V
Mode register set (MR0–MR6) L Register H L L L L L Data
  • Signal level
    • H, high
    • L, low
    • V, either low or high, a valid signal
    • X, irrelevant
  • Logic level
    • Active
    • Inactive
    • Not interpreted

Although it still operates in fundamentally the same way, DDR4 makes one major change to thecommand formats used by previous SDRAM generations.A new command signal,ACT,is low to indicate the activate (open row) command.

The activate command requires more address bits than any other (18 row address bits in a 16 Gbit part), so the standardRAS,CAS,andWEactive lowsignals are shared with high-order address bits that are not used whenACTis high. The combination ofRAS=L andCAS=WE=H that previously encoded an activate command is unused.

As in previous SDRAM encodings, A10 is used to select command variants: auto-precharge on read and write commands, and one bank vs. all banks for the precharge command. It also selects two variants of the ZQ calibration command.

As in DDR3, A12 is used to requestburst chop:truncation of an 8-transfer burst after four transfers. Although the bank is still busy and unavailable for other commands until eight transfer times have elapsed, a different bank can be accessed.

Also, the number of bank addresses has been increased greatly. There are four bank select bits to select up to 16 banks within each DRAM: two bank address bits (BA0, BA1), and two bank group bits (BG0, BG1). There are additional timing restrictions when accessing banks within the same bank group; it is faster to access a bank in a different bank group.

In addition, there are three chip select signals (C0, C1, C2), allowing up to eightstacked chipsto be placed inside a single DRAM package. These effectively act as three more bank select bits, bringing the total to seven (128 possible banks).

Standard transfer rates are 1600, 1866, 2133, 2400, 2666, 2933, and 3200 MT/s[49][50](12⁄15,14⁄15,16⁄15,18⁄15,20⁄15,22⁄15,and24⁄15GHz clock frequencies, double data rate), with speeds up to DDR4-4800 (2400 MHz clock) commercially available.[51]

Design considerations

[edit]

The DDR4 team atMicron Technologyidentified some key points for IC and PCB design:[52]

IC design:[52]

  • VrefDQ calibration (DDR4 "requires that VrefDQ calibration be performed by the controller" );
  • New addressing schemes ( "bank grouping",ACTto replaceRAS,CAS,andWEcommands, PAR andAlertfor error checking andDBIfor data bus inversion);
  • New power saving features (low-power auto self-refresh, temperature-controlled refresh, fine-granularity refresh, data-bus inversion, and CMD/ADDR latency).

Circuit board design:[52]

  • New power supplies (VDD/VDDQ at 1.2 V and wordline boost, known as VPP, at 2.5 V);
  • VrefDQ must be supplied internal to the DRAM while VrefCA is supplied externally from the board;
  • DQ pins terminate high using pseudo-open-drain I/O (this differs from the CA pins in DDR3 which are center-tapped to VTT).[52]

Rowhammermitigation techniques include larger storage capacitors, modifying the address lines to useaddress space layout randomizationand dual-voltage I/O lines that further isolate potential boundary conditions that might result in instability at high write/read speeds.

Modules

[edit]

Module packaging

[edit]
A 16GB[1]DDR4 SO-DIMM module byMicron

DDR4 memory is supplied in 288-pindual in-line memory modules(DIMMs), similar in size to 240-pin DDR3 DIMMs.DDR4 RAMmodules feature pins that are spaced more closely at0.85 mmcompared to the1.0 mmspacing in DDR3, allowing for a higher pin density within the same standardDIMMlength of133.35 mm(5¼ inches). The height of DDR4 modules is slightly increased to31.25 mm(1.23 inches) from30.35 mm(1.2 inches) to facilitate easier signal routing. Additionally, the thickness of DDR4 modules has been increased to1.2 mmfrom1.0 mmto support more signal layers, enhancing overall performance and reliability.[53]DDR4 DIMM modules have a slightly curvededge connectorso not all of the pins are engaged at the same time during module insertion, lowering the insertion force.[13]

DDR4SO-DIMMshave 260 pins instead of the 204 pins of DDR3 SO-DIMMs, spaced at 0.5 rather than 0.6 mm, and are 2.0 mm wider (69.6 versus 67.6 mm), but remain the same 30 mm in height.[54]

For itsSkylake microarchitecture,Intel designed a SO-DIMM package namedUniDIMM,which can be populated with either DDR3 or DDR4 chips. At the same time, theintegrated memory controller(IMC) of Skylake CPUs is announced to be capable of working with either type of memory. The purpose of UniDIMMs is to help in the market transition from DDR3 to DDR4, where pricing and availability may make it undesirable to switch the RAM type. UniDIMMs have the same dimensions and number of pins as regular DDR4 SO-DIMMs, but the edge connector's notch is placed differently to avoid accidental use in incompatible DDR4 SO-DIMM sockets.[55]

JEDEC standard DDR4 module

[edit]
Standard
name 		Memory
clock
(MHz) 		I/O bus
clock
(MHz) 		Data
rate
(MT/s)[b] 		Module
name 		Peak trans-
fer rate
(GB/s)[c] 		Timings
CL-tRCD-tRP 		CAS
latency
(ns)
DDR4-1600J*
DDR4-1600K
DDR4-1600L		 200 800 1600 PC4-12800 12.8 10-10-10
11-11-11
12-12-12		 12.5
13.75
15
DDR4-1866L*
DDR4-1866M
DDR4-1866N		 233.33 933.33 1866.67 PC4-14900 14.9333 12-12-12
13-13-13
14-14-14		 12.857
13.929
15
DDR4-2133N*
DDR4-2133P
DDR4-2133R		 266.67 1066.67 2133.33 PC4-17000 17.06667 14-14-14
15-15-15
16-16-16		 13.125
14.063
15
DDR4-2400P*
DDR4-2400R
DDR4-2400T
DDR4-2400U		 300 1200 2400 PC4-19200 19.2 15-15-15
16-16-16
17-17-17
18-18-18		 12.5
13.32
14.16
15
DDR4-2666T
DDR4-2666U
DDR4-2666V
DDR4-2666W		 333.33 1333.33 2666.67 PC4-21300 21.3333 17-17-17
18-18-18
19-19-19
20-20-20		 12.75
13.50
14.25
15
DDR4-2933V
DDR4-2933W
DDR4-2933Y
DDR4-2933AA		 366.67 1466.67 2933.33 PC4-23466 23.46667 19-19-19
20-20-20
21-21-21
22-22-22		 12.96
13.64
14.32
15
DDR4-3200W
DDR4-3200AA
DDR4-3200AC		 400 1600 3200 PC4-25600 25.6 20-20-20
22-22-22
24-24-24		 12.5
13.75
15
CAS latency(CL)
Clock cyclesbetween sending a column address to the memory and the beginning of the data in response
tRCD
Clock cycles between row activate and reads/writes
tRP
Clock cycles between row precharge and activate

DDR4-xxxx denotes per-bit data transfer rate, and is normally used to describe DDR chips. PC4-xxxxx denotes overall transfer rate, in megabytes per second, and applies only to modules (assembled DIMMs). Because DDR4 memory modules transfer data on a bus that is 8 bytes (64 data bits) wide, module peak transfer rate is calculated by taking transfers per second and multiplying by eight.[56]

Successor

[edit]

At the 2016Intel Developer Forum,the future ofDDR5 SDRAMwas discussed. The specifications were finalized at the end of 2016 – but no modules will be available before 2020.[57]Other memory technologies – namelyHBMin version 3 and 4[58]– aiming to replace DDR4 have also been proposed.

In 2011, JEDEC introduced theWide I/O 2standard, which features stacked memory dies placed directly on top of the CPU within the same package. This configuration provides higher bandwidth and improved power efficiency compared to DDR4 SDRAM, thanks to its wide interface and short signal lengths. Wide I/O 2 aims to replace various mobileDDRX SDRAMstandards used in high-performance embedded and mobile devices like smartphones.

In parallel, Hynix developedHigh Bandwidth Memory(HBM),standardized as JEDEC JESD235. Both Wide I/O 2 and HBM utilize a very wide parallel memory interface—up to 512 bits for Wide I/O 2 compared to 64 bits for DDR4—although they operate at lower frequencies than DDR4. Wide I/O 2 is designed for high-performance, compact devices, often integrated into processors or system on a chip (SoC) packages. In contrast, HBM targets graphics memory and general computing, whileHybrid Memory Cube(HMC)is aimed at high-end servers and enterprise applications.[59]

Micron Technology'sHybrid Memory Cube(HMC) stacked memory uses a serial interface. Many other computer buses have migrated towards replacing parallel buses with serial buses, for example by the evolution ofSerial ATAreplacingParallel ATA,PCI ExpressreplacingPCI,and serial ports replacing parallel ports. In general, serial buses are easier to scale up and have fewer wires/traces, making circuit boards using them easier to design.[60][61][62]

In the longer term, experts speculate that non-volatile RAM types like PCM (phase-change memory), RRAM (resistive random-access memory), or MRAM (magnetoresistive random-access memory) could replace DDR4 SDRAM and its successors.[63]

GDDR5SGRAM is a graphics type ofDDR3synchronous graphics RAM,which was introduced before DDR4, and is not a successor to DDR4.

See also

[edit]

Notes

[edit]
  1. ^As a prototype, this DDR4 memory module has a flatedge connectorat the bottom, while production DDR4 DIMM modules have a slightly curved edge connector so not all of the pins are engaged at a time during module insertion, lowering the insertion force.[13]
  2. ^1 MT = one million transfers
  3. ^1 GB = one billion bytes

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[edit]
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