Datapath
Adata pathis a collection offunctional unitssuch asarithmetic logic units(ALUs) ormultipliersthat perform data processing operations,registers,andbuses.[1]Along with thecontrol unitit composes thecentral processing unit (CPU).[1]A larger data path can be made by joining more than one data paths usingmultiplexers.
Adata pathis the ALU, the set of registers, and the CPU's internal bus(es) that allow data to flow between them.[2]
The simplest design for a CPU uses one common internal bus. Efficient addition requires a slightly more complicated three-internal-bus structure.[3] Many relatively simple CPUs have a 2-read, 1-writeregister file connected to the 2 inputs and 1 output of the ALU.
During the late 1990s, there was growing research in the area ofreconfigurabledata paths—data paths that may be re-purposed at run-time usingprogrammable fabric—as such designs may allow for more efficient processing as well as substantial power savings.[4]
Finite state machine with data path[edit]
Afinite-state machine with data path(FSMD) is a mathematical abstraction which combines afinite-state machine,which controls theprogram flow,with a data path. It can be used to designdigital logicorcomputer programs.[5][6]
FSMDs are essentially sequential programs in which statements have been scheduled into states, thus resulting in more complex state diagrams. Here, a program is converted into a complex state diagram in which states and arcs may includearithmetic expressions,and those expressions may use external inputs and outputs as well as variables. The FSMD level of abstraction is often referred to as theregister-transfer level.
FSMs do not use variables or arithmetic operations/conditions, thus FSMDs are more powerful than FSMs. An FSMD is equivalent to aTuring machinein expressiveness.
References[edit]
- ^abNull, Linda; Lobur, Julia (2006).The Essentials of Computer Organization and Architecture.Jones & Bartlett Learning. p. 2016.ISBN978-0-7637-3769-6.
All computers have a CPU that can be divided into two pieces. The first is the datapath, which is a network of storage units (registers) and arithmetic and logic units... connected by buses... where the timing is controlled by clocks.
- ^ Edward Bosworth. "Overview of Computer Architecture".
- ^ Edward Bosworth. "CPU Bus Structure".
- ^J. R. Hauser and J. Wawrzynek,Garp: a MIPS processor with a reconfigurable coprocessor,FCCM’97, 1997, pp. 12–21.Archived2017-09-22 at theWayback Machine
- ^Zhu, Jianwen; Gajski, Daniel D. (1999-03-01). "A unified formal model of ISA and FSMD".Proceedings of the seventh international workshop on Hardware/Software codesign - CODES '99.CODES '99. New York, NY, USA: Association for Computing Machinery. pp. 121–125.doi:10.1145/301177.301504.ISBN978-1-58113-132-1.S2CID5426988.
- ^Hsu, Y.C.; Liu, T.Y.; Tsai, F.S.; Lin, S.Z.; Yu, C. (1994-12-05)."Digital design from concept to prototype in hours".Proceedings of APCCAS'94 - 1994 Asia Pacific Conference on Circuits and Systems.pp. 175–181.doi:10.1109/APCCAS.1994.514545.ISBN0-7803-2440-4.S2CID61056791.