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Fin field-effect transistor

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This article is about fin-shaped field-effect transistor. For Ferroelectric memory with a ferroelectric FET gate, seeFeFET.
A double-gate FinFET device

Afin field-effect transistor(FinFET) is amultigate device,aMOSFET(metal–oxide–semiconductorfield-effect transistor) built on asubstratewhere the gate is placed on two, three, or four sides of the channel or wrapped around the channel (gate all around), forming a double or even multi gate structure. These devices have been given the generic name "FinFETs" because the source/drain region forms fins on the silicon surface. The FinFET devices have significantly fasterswitching timesand highercurrent densitythan planarCMOS(complementary metal–oxide–semiconductor) technology.[1]

FinFET is a type of non-planartransistor,or "3D" transistor.[2]It is the basis for modernnanoelectronicsemiconductor device fabrication.Microchips utilizing FinFET gates first became commercialized in the first half of the 2010s, and became the dominant gate design at14 nm,10 nmand7 nmprocessnodes.

It is common for a single FinFET transistor to contain several fins, arranged side by side and all covered by the same gate, that act electrically as one. The number of fins can be varied to adjust drive strength and performance,[3]with drive strength increasing with a higher number of fins.[4]

History[edit]

After the MOSFET was first demonstrated byMohamed AtallaandDawon KahngofBell Labsin 1960,[5]the concept of adouble-gatethin-film transistor(TFT) was proposed by H. R. Farrah (Bendix Corporation) and R. F. Steinberg in 1967.[6]A double-gate MOSFET was later proposed by Toshihiro Sekigawa of theElectrotechnical Laboratory(ETL) in a 1980patentdescribing the planar XMOS transistor.[7]Sekigawa fabricated the XMOS transistor with Yutaka Hayashi at the ETL in 1984. They demonstrated thatshort-channel effectscan be significantly reduced by sandwiching a fully depletedsilicon-on-insulator(SOI) device between twogate electrodesconnected together.[8][9]

The first FinFET transistor type was called a "Depleted Lean-channel Transistor" (DELTA) transistor, which was first fabricated in Japan byHitachi Central Research Laboratory's Digh Hisamoto, Toru Kaga, Yoshifumi Kawamoto and Eiji Takeda in 1989.[8][10][11]The gate of the transistor can cover and electrically contact the semiconductor channel fin on both the top and the sides or only on the sides. The former is called atri-gate transistorand the latter adouble-gate transistor.A double-gate transistor optionally can have each side connected to two different terminal or contacts. This variant is calledsplit transistor.This enables more refined control of the operation of the transistor.

Indonesian engineer Effendi Leobandung, while working at theUniversity of Minnesota,published a paper with Stephen Y. Chou at the 54th Device Research Conference in 1996 outlining the benefit of cutting a wideCMOStransistor into many channels with narrow width to improve device scaling and increase device current by increasing the effective device width.[12]This structure is what a modern FinFET looks like. Although some device width is sacrificed by cutting it into narrow widths, the conduction of the side wall of narrow fins more than make up for the loss, for tall fins.[13][14]The device had a35 nmchannel width and70 nmchannel length.[12]

The potential of Digh Hisamoto's research on DELTA transistors drew the attention of theDefense Advanced Research Projects Agency(DARPA), which in 1997 awarded a contract to a research group at theUniversity of California, Berkeleyto develop a deepsub-microntransistor based on DELTA technology.[15]The group was led by Hisamoto along withTSMC'sChenming Hu.The team made the following breakthroughs between 1998 and 2004.[16]

  • 1998 –N-channelFinFET (17 nm) – Digh Hisamoto, Chenming Hu,Tsu-Jae King Liu,Jeffrey Bokor, Wen-Chin Lee, Jakub Kedzierski, Erik Anderson, Hideki Takeuchi, Kazuya Asano[17]
  • 1999 –P-channelFinFET (sub-50 nm) – Digh Hisamoto, Chenming Hu, Xuejue Huang, Wen-Chin Lee, Charles Kuo, Leland Chang, Jakub Kedzierski, Erik Anderson, Hideki Takeuchi[18]
  • 2001 –15 nmFinFET – Chenming Hu, Yang-Kyu Choi, Nick Lindert, P. Xuan, S. Tang, D. Ha, Erik Anderson, Tsu-Jae King Liu, Jeffrey Bokor[19]
  • 2002 –10 nmFinFET – Shibly Ahmed, Scott Bell, Cyrus Tabery, Jeffrey Bokor, David Kyser, Chenming Hu, Tsu-Jae King Liu, Bin Yu, Leland Chang[20]
  • 2004 –High-κ/metal gateFinFET – D. Ha, Hideki Takeuchi, Yang-Kyu Choi, Tsu-Jae King Liu, W. Bai, D.-L. Kwong, A. Agarwal, M. Ameen

They coined the term "FinFET" (fin field-effect transistor) in a December 2000 paper,[21]used to describe a non-planar, double-gate transistor built on an SOI substrate.[22]

In 2006, a team of Korean researchers from theKorea Advanced Institute of Science and Technology(KAIST) and the National Nano Fab Center developed a3 nmtransistor, the world's smallestnanoelectronicdevice, based ongate-all-around(GAA) FinFET technology.[23][24]In 2011,Rice Universityresearchers Masoud Rostami and Kartik Mohanram demonstrated that FinFETs can have two electrically independent gates, which gives circuit designers more flexibility to design with efficient, low-power gates.[25]

In 2020, Chenming Hu received theIEEE Medal of Honoraward for his development of the FinFET, which theInstitute of Electrical and Electronics Engineers(IEEE) credited with taking transistors to the third dimension and extendingMoore's law.[26]

Commercialization[edit]

The industry's first 25 nanometer transistor operating on just 0.7voltswas demonstrated in December 2002 byTSMC.The "Omega FinFET" design, named after the similarity between the Greek letter "Omega"and the shape in which the gate wraps around the source/drain structure, has agate delayof just 0.39picosecond(ps) for the N-type transistor and 0.88 ps for the P-type.

In 2004,Samsungdemonstrated a "Bulk FinFET" design, which made it possible to mass-produce FinFET devices. They demonstrated dynamicrandom-access memory(DRAM) manufactured with a90nmBulk FinFET process.[16]

In 2011,Inteldemonstratedtri-gate transistors,where the gate surrounds the channel on three sides, allowing for increased energy efficiency and lower gate delay—and thus greater performance—over planar transistors.[27][28][29]

Commercially produced chips at22 nmand below have generally utilised FinFET gate designs (but planar processes do exist down to 18 nm, with 12 nm in development). Intel'stri-gatevariant were announced at 22 nm in 2011 for itsIvy Bridge microarchitecture.[30]These devices shipped from 2012 onwards. From 2014 onwards, at14 nm(or 16 nm) major foundries (TSMC, Samsung,GlobalFoundries) utilised FinFET designs.

In 2013,SK Hynixbegan commercial mass-production of a 16nm process,[31]TSMC began production of a 16nm FinFET process,[32]andSamsung Electronicsbegan production of a10nmprocess.[33]TSMC began production of a7 nmprocess in 2017,[34]and Samsung began production of a5 nmprocess in 2018.[35]In 2019, Samsung announced plans for the commercial production of a 3nmGAAFETprocess by 2021.[36]FD-SOI (Fully DepletedSilicon On Insulator) has been seen as a potential low cost alternative to FinFETs.[37]


Commercial production ofnanoelectronicFinFETsemiconductor memorybegan in the 2010s.[1]In 2013, SK Hynix began mass-production of 16nmNAND flashmemory,[31]and Samsung Electronics began production of10nmmulti-level cell(MLC) NAND flash memory.[33]In 2017, TSMC began production ofSRAMmemory using a 7 nm process.[34]

See also[edit]

References[edit]

  1. ^abKamal, Kamal Y. (2022)."The Silicon Age: Trends in Semiconductor Devices Industry"(PDF).Journal of Engineering Science and Technology Review.15(1): 110–115.doi:10.25103/jestr.151.14.ISSN1791-2377.S2CID249074588.Retrieved2022-05-26.
  2. ^"What is Finfet?".Computer Hope.April 26, 2017.Retrieved4 July2019.
  3. ^Shimpi, Anand Lal (4 May 2011)."Intel Announces first 22nm 3D Tri-Gate Transistors, Shipping in 2H 2011".AnandTech.Retrieved18 January2022.
  4. ^"VLSI Symposium - TSMC and Imec on Advanced Process and Devices Technology Toward 2nm".25 February 2024.
  5. ^"1960: Metal Oxide Semiconductor (MOS) Transistor Demonstrated".The Silicon Engine.Computer History Museum.Retrieved25 September2019.
  6. ^Farrah, H. R.; Steinberg, R. F. (February 1967). "Analysis of double-gate thin-film transistor".IEEE Transactions on Electron Devices.14(2): 69–74.Bibcode:1967ITED...14...69F.doi:10.1109/T-ED.1967.15901.
  7. ^Koike, Hanpei; Nakagawa, Tadashi; Sekigawa, Toshiro; Suzuki, E.; Tsutsumi, Toshiyuki (23 February 2003). "Primary Consideration on Compact Modeling of DG MOSFETs with Four-terminal Operation Mode".TechConnect Briefs.2(2003): 330–333.S2CID189033174.
  8. ^abColinge, J. P. (2008).FinFETs and Other Multi-Gate Transistors.Springer Science & Business Media. pp. 11 & 39.ISBN9780387717517.
  9. ^Sekigawa, Toshihiro; Hayashi, Yutaka (August 1984). "Calculated threshold-voltage characteristics of an XMOS transistor having an additional bottom gate".Solid-State Electronics.27(8): 827–828.Bibcode:1984SSEle..27..827S.doi:10.1016/0038-1101(84)90036-4.ISSN0038-1101.
  10. ^Hisamoto, Digh; Kaga, Toru; Kawamoto, Yoshifumi; Takeda, Eiji (December 1989). "A fully depleted lean-channel transistor (DELTA)-a novel vertical ultra thin SOI MOSFET".International Technical Digest on Electron Devices Meeting.pp. 833–836.doi:10.1109/IEDM.1989.74182.S2CID114072236.
  11. ^"IEEE Andrew S. Grove Award Recipients".IEEE Andrew S. Grove Award.Institute of Electrical and Electronics Engineers.Retrieved4 July2019.
  12. ^abLeobandung, Effendi; Chou, Stephen Y. (1996). "Reduction of short channel effects in SOI MOSFETs with 35 nm channel width and 70 nm channel length".1996 54th Annual Device Research Conference Digest.pp. 110–111.doi:10.1109/DRC.1996.546334.ISBN0-7803-3358-6.S2CID30066882.
  13. ^Leobandung, Effendi (June 1996).Nanoscale MOSFETs and single charge transistors on SOI(Ph.D. thesis). Minneapolis, Minnesota: University of Minnesota. p. 72.
  14. ^Leobandung, Effendi; Gu, Jian; Guo, Lingjie; Chou, Stephen Y. (1997-11-01)."Wire-channel and wrap-around-gate metal–oxide–semiconductor field-effect transistors with a significant reduction of short channel effects".Journal of Vacuum Science & Technology B: Microelectronics and Nanometer Structures Processing, Measurement, and Phenomena.15(6): 2791–2794.Bibcode:1997JVSTB..15.2791L.doi:10.1116/1.589729.ISSN1071-1023.
  15. ^"The Breakthrough Advantage for FPGAs with Tri-Gate Technology"(PDF).Intel.2014.Retrieved4 July2019.
  16. ^abTsu-Jae King, Liu(June 11, 2012)."FinFET: History, Fundamentals and Future".University of California, Berkeley.Symposium on VLSI Technology Short Course.Archivedfrom the original on 28 May 2016.Retrieved9 July2019.
  17. ^Hisamoto, Digh; Hu, Chenming; Liu, Tsu-Jae King; Bokor, Jeffrey; Lee, Wen-Chin; Kedzierski, Jakub; Anderson, Erik; Takeuchi, Hideki; Asano, Kazuya (December 1998). "A folded-channel MOSFET for deep-sub-tenth micron era".International Electron Devices Meeting 1998. Technical Digest (Cat. No.98CH36217).pp. 1032–1034.doi:10.1109/IEDM.1998.746531.ISBN0-7803-4774-9.S2CID37774589.
  18. ^Hisamoto, Digh; Kedzierski, Jakub; Anderson, Erik; Takeuchi, Hideki (December 1999)."Sub 50-nm FinFET: PMOS"(PDF).International Electron Devices Meeting 1999. Technical Digest (Cat. No.99CH36318).pp. 67–70.doi:10.1109/IEDM.1999.823848.ISBN0-7803-5410-9.S2CID7310589.Archived fromthe original(PDF)on 2010-06-06.Retrieved2019-09-25.
  19. ^Hu, Chenming;Choi, Yang-Kyu; Lindert, N.; Xuan, P.; Tang, S.; Ha, D.; Anderson, E.; Bokor, J.; Tsu-Jae King, Liu (December 2001). "Sub-20 nm CMOS FinFET technologies".International Electron Devices Meeting. Technical Digest (Cat. No.01CH37224).pp. 19.1.1–19.1.4.doi:10.1109/IEDM.2001.979526.ISBN0-7803-7050-3.S2CID8908553.
  20. ^Ahmed, Shibly; Bell, Scott; Tabery, Cyrus; Bokor, Jeffrey; Kyser, David; Hu, Chenming; Liu, Tsu-Jae King; Yu, Bin; Chang, Leland (December 2002)."FinFET scaling to 10 nm gate length"(PDF).Digest. International Electron Devices Meeting.pp. 251–254.CiteSeerX10.1.1.136.3757.doi:10.1109/IEDM.2002.1175825.ISBN0-7803-7462-2.S2CID7106946.Archived fromthe original(PDF)on 2020-05-27.Retrieved2019-09-25.
  21. ^Hisamoto, Digh;Hu, Chenming;Bokor, J.; King, Tsu-Jae; Anderson, E.; et al. (December 2000). "FinFET—a self-aligned double-gate MOSFET scalable to 20 nm".IEEE Transactions on Electron Devices.47(12): 2320–2325.Bibcode:2000ITED...47.2320H.CiteSeerX10.1.1.211.204.doi:10.1109/16.887014.
  22. ^Hisamoto, Digh;Hu, Chenming;Huang, Xuejue; Lee, Wen-Chin; Kuo, Charles; et al. (May 2001)."Sub-50 nm P-channel FinFET"(PDF).IEEE Transactions on Electron Devices.48(5): 880–886.Bibcode:2001ITED...48..880H.doi:10.1109/16.918235.
  23. ^"Still Room at the Bottom.(nanometer transistor developed by Yang-kyu Choi from the Korea Advanced Institute of Science and Technology )",Nanoparticle News,1 April 2006, archived fromthe originalon 6 November 2012,retrieved6 July2019
  24. ^Lee, Hyunjin; et al. (2006). "Sub-5nm All-Around Gate FinFET for Ultimate Scaling".2006 Symposium on VLSI Technology, 2006. Digest of Technical Papers.pp. 58–59.doi:10.1109/VLSIT.2006.1705215.hdl:10203/698.ISBN978-1-4244-0005-8.S2CID26482358.
  25. ^Rostami, M.; Mohanram, K. (2011)."Dual-VthIndependent-Gate FinFETs for Low Power Logic Circuits "(PDF).IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.30(3): 337–349.doi:10.1109/TCAD.2010.2097310.hdl:1911/72088.S2CID2225579.
  26. ^"How the Father of FinFETs Helped Save Moore's Law: Chenming Hu, the 2020 IEEE Medal of Honor recipient, took transistors into the third dimension".IEEE Spectrum.21 April 2020.Retrieved27 December2021.
  27. ^Bohr, Mark; Mistry, Kaizad (May 2011)."Intel's Revolutionary 22 nm Transistor Technology"(PDF).intel.com.RetrievedApril 18,2018.
  28. ^Grabham, Dan (May 6, 2011)."Intel's Tri-Gate transistors: everything you need to know".TechRadar.RetrievedApril 19,2018.
  29. ^ Bohr, Mark T.; Young, Ian A. (2017). "CMOS Scaling Trends and Beyond".IEEE Micro.37(6): 20–29.doi:10.1109/MM.2017.4241347.S2CID6700881.The next major transistor innovation was the introduction of FinFET (tri-gate) transistors on Intel's 22-nm technology in 2011.
  30. ^"Intel 22nm 3-D Tri-Gate Transistor Technology".Intel Newsroom.
  31. ^ab"History: 2010s".SK Hynix.Archived fromthe originalon 17 May 2021.Retrieved8 July2019.
  32. ^"16/12nm Technology".TSMC.Retrieved30 June2019.
  33. ^ab"Samsung Mass Producing 128Gb 3-bit MLC NAND Flash".Tom's Hardware.11 April 2013. Archived fromthe originalon 21 June 2019.Retrieved21 June2019.
  34. ^ab"7nm Technology".TSMC.Retrieved30 June2019.
  35. ^Shilov, Anton."Samsung Completes Development of 5nm EUV Process Technology".www.anandtech.com.Retrieved2019-05-31.
  36. ^Armasu, Lucian (11 January 2019),"Samsung Plans Mass Production of 3nm GAAFET Chips in 2021",www.tomshardware.com
  37. ^"Samsung, GF Ramp FD-SOI".27 April 2018.

External links[edit]

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