Jump to content

GEC 4000 series

Edit links
From Wikipedia, the free encyclopedia

GEC 4000 series computers at GEC Computers' Dunstable Development Centre, 1991
GEC 4080 front panel[1]

TheGEC 4000was a series of16/32-bitminicomputersproduced byGEC Computers Ltdin the United Kingdom during the 1970s, 1980s and early 1990s.

History[edit]

GEC Computerswas formed in 1968 as a business unit of theGECconglomerate. It inherited fromElliott Automationthe ageing Elliott 900 series, and needed to develop a new range of systems. Three ranges were identified, known internally as Alpha, Beta, and Gamma. Alpha appeared first and became theGEC 20508-bit minicomputer. Beta followed and became the GEC 4080. Gamma was never developed, so a few of its enhanced features were consequently pulled back into the 4080. The principal designer of the GEC 4080 was Dr. Michael Melliar-Smith and the principal designer of the 4060 and 4090 was Peter Mackley.

The 4000 series systems were developed and manufactured in the UK at GEC Computers'Borehamwoodoffices in Elstree Way. Development and manufacture transferred to the company's new factories in Woodside Estate,Dunstablein the late 1970s. In 1979, GEC Computers was awarded theQueen's Award for Technical Achievementfor the development of the 4000 series, particularly Nucleus.[2]By 1991, the number of systems manufactured was falling off, so manufacture was transferred toGPT'sBeeston, Nottinghamshirefactory and development returned to Borehamwood. The last systems were manufactured around 1995. There were still a few GEC 4220 systems operating in 2018 with maintenance provided byTelent,and some GEC 4310 were operating until 2013.London Undergroundcontinues to use GEC 4190 systems in 2022.

Nucleus[edit]

The GEC 4000 serieshardwareandfirmwareincluded a pioneering facility known asNucleus.[3]Nucleus implements a number of features which are more usually implemented within anoperating systemkernel,and consequently operating systems running on GEC 4000 series systems do not need to directly provide these features themselves. Nucleus firmware cannot be reprogrammed by any code running on the system, and this made the systems particularly attractive to a number of security applications.

Nucleus performs:[4]

There is no provision for running any supervisor/privileged/kernel mode code on the 4000 systems—all operating system code runs as processes. Hence,device drivers,file systemcode, and other features which are often found within operating system kernels must be run in processes on the 4000 systems. Inherent in this is that they are all running in their own address spaces, protected from the actions of each other, just as all processes are.

Nucleus is configured by a set of system tables, and processes which have a need to modify the operation of nucleus are given access to the relevant system tables. This would be the case for processes which directly change the state of other processes, processes which allocate and delete memory segments, processes which can change the routing of messages between other processes or change the mapping of I/O devices to processes, etc. Normally system table access is limited to relatively few trusted processes, and other processes which need to perform operations such as loading processes, allocating memory, etc. will pass a message to the relevant trusted process which it will vet before performing the action and replying.

Instruction set[edit]

The 4000 series has aCISCinstruction set.It has8-bitbytes,big-endian,byte-addressablememory,two's complementarithmetic, andbase-16 excess-64 floating point format(same asIBM System/360).[5]

The model numbers below 4090 are 16-bit processors, and model numbers from 4090 upwards are mixed 16-bit and 32-bit. This relates to pointer sizes available to programs. All systems support 16-bit pointers, which is known as CST (Current Segment Table) addressing. The 32-bit systems also support 32-bit pointers, known as PAS (Paged Address Space) addressing. Each process has a PAST (Program Accessible Segment Table) which lists which of the system's memory segments the program is permitted to access. CST addressing allows four of the PAST entries to be mapped at addresses 0, 16KiB, 32KiB, and 48KiB, giving the 16-bit/64KiB address space. Programs which use more than 64KiB of memory must explicitly map the PAST entries they require at any moment into their 4 CST entries, although Nucleus will automatically map different code segments into the CSTs. PAS addressing allows programs to view their address space as a flat 32-bit address space, with successive PAST entries appearing every 16KiB, and Nucleus performing the PAST entry segment mapping automatically. The 32-bit systems support mixing of CST and PAS addressing in the same process. All instructions are 16 bits wide, except for some PAS addressing instructions which are 32 bits. Instructions can only be run from CST address space.

The 32-bit A register is the main accumulator register. There is a 32-bit B register too, which is most commonly used together with the A register as a 64-bit BA register for double-precision floating point operations. A 16-bit X register is used mainly for array indexing, and two 16-bit Y and Z registers are used as 16-bit pointers. A 16-bit L register points to function local data, and a G register always contains zero which can be used as a 16-bit global pointer, and also an 8-bit, 16-bit, or 32-bit zero value. The 16-bit S (sequence) register points to the next instruction to be obeyed. The 8-bit EC register contains condition codes bits. (Some of this is illustrated in the much simpler instruction set of theGEC 2050.) A read-only 'keys' register allows programs to read the value set on the front panel toggle switches by the operations staff. No 32-bit PAS pointer register exists—32-bit PAS pointers reside in memory in the 16-bit CST address space, and are accessed by using a 16-bit pointer. There is no instruction set support for astack.There are a number of registers inaccessible to programs which are used by Nucleus, such as the hardware segment registers which point to the running process's four CSTs, master segment and PAS segments, and the system tables.

The instruction set contains instructions which operate register-register, store-register, register-store, and store-store. There are a set of string manipulation instructions which operate on variable lengths of store, copying, comparing, or scanning for a pattern. There are a number of Nucleus instructions for tasks such as sending a message to another process or a peripheral device, receiving a message or interrupt, changing a CST entry to point to a different segment which is accessible to the process, etc.

The 4080 has a two-stageinstruction pipeline.This becomes a four-stage pipeline for the 4220, the highest-performing system in the series. The entry-level 415x and 4x6x systems have only a single-stage pipeline.

The normal operating mode of the CPU is calledFull Nucleus.All systems also support a limited mode of operation calledBasic Test.In Basic Test mode, Nucleus is disabled, I/O is performed differently, and only a single program can run, restricted to the bottom 64KiB of store, but all other non-nucleus and non-PAS instructions operate normally. This mode is used very early during booting to set up the system tables required by Nucleus, before obeying aSwitch Full Nucleusinstruction. Once the system has switched to Full Nucleus, it cannot return to Basic Test mode without operator intervention at the front panel, in effect killing any operating system which was running. Basic Test mode is also used to run certain test software (hence the name).

Input/output[edit]

The 4000 I/O design is based around a number ofInput/Output Processorsknown asIOPs,each of which interfaces between the store and a set of I/O controllers. The IOPs are controlled by the Nucleus function in the CPU, but once an I/O event is triggered, they operate autonomously without interaction with the CPU until the I/O completes. TheNormal InterfaceIOPs can each support up to 255 or 256 simultaneous I/O operations, each on a separateWay.The I/O controllers on each IOP would each occupy one or more Ways, depending on how many simultaneous I/O operations they need to handle. The IOP polices each Way's access to main store, allowing only access to successive memory locations defined for the I/O operation that Way is currently performing. The earlier IOPs performed 8-bit and 16-bit wide store accesses, with a burst mode for doing up to 8 transfers together for higher throughput I/O controllers. The later IOPs added 32-bit wide store accesses.

All systems have at least one IOP. On the 4080, this first IOP was called the Basic Multiplexer Channel,[6]or BMC, and the 4080 front panel provides for controlling both the CPU and the BMC. The entry level 415x and 4x6x systems have their first IOP (Integral Multiplexer Channel, or IMC) integrated into the Nucleus firmware, and thus I/O operations on the IMC did have some impact on CPU performance, although the 4x6x systems could have external IOPs added. The 4000 series Nucleus I/O instructions and system tables allow for up to 8 IOPs, although most of the models in the 4000 series range had some type of hardware limitation which reduced this. The 408x systems had 4-ported store, with the CPU and first IOP sharing one of these, and up to three additional IOPs connected to the remaining store ports. (Early documentation shows these additional store ports were also designed to connect additional CPUs, although this was not a configuration which was ever sold using 4080 processors.) Later models had more store ports, depending on how many store port boards could be fitted into the system. The 4190 could support the full complement of eight IOPs, and the 4190D supported eight IOPs with two CPUs.

Some commonly used I/O Controllers are theinterval timer,system consolecontroller,punched tapereader and punch controllers,line printercontroller (all these use a single Way), a number ofSMD(and earlierdiskbus interface) disk controllers for controlling up to four drives (all using two Ways),PertecPPCmagnetic tapecontrollers for up to four1⁄2"tape drives, and a number of multi-portedsynchronousandasynchronousserial communicationcontrollers (using between 4 and 32 Ways). A digital I/O board (using four Ways) was commonly used for direct process control interfacing, and for providing a fast parallel link between systems. ACAMACcrate controller was also available (again, used for process control interfacing). The Normal Interface bus which these controllers plug into is a published interface,[7]and many customers also built their own controllers for their own specific process control requirements. The earlier GEC 2050 minicomputer used an 8-bit version of the Normal Interface, and most I/O Controllers could be used on both ranges of systems.

All the IOPs designed and built through the 1970s provided the same Normal Interface bus for I/O Controllers, and the I/O controllers could generally be used in any of them. In the 1980s, some more specialised IOPs were designed. A Direct Memory Access Director (DMAD) IOP allowed for a new type of I/O controller which had more freedom to access main memory, and allowed the design of more intelligent communications controllers. ASCSIIOP generated a SCSI bus for attaching more modern disks, and also included an integrated Interval Timer, system console controller, and Calendar Clock so that an additional Normal Interface IOP and separate controllers was not required to support just these functions.

Customers[edit]

Users of GEC 4000 series systems included many British university physics and engineering departments, the central computing service ofUniversity College London(Euclid) andKeele University,theJANETacademic/research networkX.25switching backbone,Rutherford-Appleton Laboratory,[8]Daresbury Laboratory,Harwell Laboratory,NERC,Met Office,CERN,ICI,British Telecom,SIP(Italiantelco), andPlessey.British Steel CorporationandBHP Steelused them for real-time control of rolling steel mills,British RailandLondon Undergroundfor real-time train scheduling,London Fire Brigadeand Durham Fire Brigade for command and control systems. The computers controlled most of the world's nationalVideotexsystems, including thePrestelviewdataservice.

At the Rutherford-Appleton Laboratory a GEC 4000 system was used to control the synchrotron and injectors used for theISISneutronspallation source until 1998.

A GEC 4080M was used as the central processor for the radar system of the ill-fatedNimrod AEW.3airborne early warningaircraft.[9]

TheCentral Electricity Generating Boardused GEC 4080 processors at three of their Grid Control Centres. Known as GI74, they were used to collect data from substations and display this on the wall diagrams and tabular VDUs.

Models[edit]

A number of variants of the GEC 4000 processor were produced, including (in approximate chronological order):

  • 4080:original 1973 model with 64–256 KiB ofcore memory
  • 4082:4080 with up to 1 MiB of memory
  • 4070:entry-level model without memory interleaving
  • 4085:4082 withsemiconductormemory
  • 4060:entry-level model based onAMDAm2900bit-sliceprocessors
  • 4062/4065:4060 supporting up to 1 MiB memory
  • 4080M:compact ruggedised 4080 for military applications
  • 4090:Am2900-based with 32-bit addressing extensions and up to 4 MiB of memory
  • 4190:revised 4090 with up to 16 MiB memory
  • 4180:cheaper, slower version of the 4190 (no memory cache, no fast multiply unit)
  • 4060M:compact ruggedised 4060 for military applications
  • 4160:4065 with the 4090 32-bit addressing extensions
  • 4150:desktop 4160
  • 4162:4160 with DMAD IOP(s) for high speed communications controllers
  • 4195:compact 4190
  • 4185:cheaper, slower version of the 4195 (no memory cache, no fast multiply unit)
  • 4151:rackmount4150
  • 4190D:dual-processor 4190
  • 4193:4195 withSCSIIOP replacing the default Normal Interface IOP
  • 4220:Reimplement 4190 usinggate arrayprocessor technology
  • 4310:Motorola 88100MVME187-based system emulating a GEC 4220

Software[edit]

Several operating systems were available for the GEC 4000 series, including:

Programming languages available includedBabbage(ahigh-level assembly language),FORTRAN IV,CORAL 66,ALGOL,APLandBASIC.

Babbage[edit]

Babbage is thehigh level assembly languagefor the GEC 4000 seriesminicomputers.It appeared in 1971.[10][11]It was named afterCharles Babbage,anEnglishcomputing pioneer.[10]

Example[edit]

This code prints thefactorialfor numbers from 1 to 9. 

PROCESS CHAPTER FACTORIAL

ENTRY LABEL ENTRYPOINT

LITERAL TO = 4 // Assume using the default proforma

EXTERNAL ROUTINE
OPEN,
PUT,
CLOSE,
TOCHAR

VECTOR [0,19] OF BYTE ANSWER = "factorial x = xxxxxx"

HALF COUNT
HALF VALUE
FULL RESULT

//******************************************************************************

ROUTINE FACT(VALUE)
// return factorial of RA.

VALUE => RESULT

WHILE DECREMENT VALUE GT //0// DO
<<
RESULT * VALUE => RESULT
>>
RETURN(RESULT)
END

//******************************************************************************

ENTRYPOINT:

OPEN(TO, 1)

// Print factorials for numbers 1 through 9
1 => RA
REPEAT
<<
RA => COUNT
FACT(RA) => RA
TOCHAR(RA, 7, ANSWER + 13)
TOCHAR(COUNT, 2, ANSWER + 9)
PUT(TO, 20, ANSWER)
COUNT + 1 => RA
>>
WHILE RA LT 10

CLOSE(TO)
STOP(0)
END

//******************************************************************************

See also[edit]

References[edit]

  1. ^"Central Processor Unit Controls and Monitoring"(PDF).GEC 4000 Computer.December 1977.Retrieved15 June2009.
  2. ^"Press Release: GEC Computers wins Queens Award"(PDF).21 April 1979. Archived fromthe original(PDF)on 22 October 2019.
  3. ^"Central Processor Unit Nucleus Manual"(PDF).GEC 4000 Computer.December 1977.Retrieved15 June2009.
  4. ^P. J. Denning, "ACM president's letter: computer architecture: some old ideas that haven't quite made it yet",Communications of the ACM,24 (9), 1981, page 553.
  5. ^"Central Processor Unit Instruction Set (GEC 4080)"(PDF).GEC 4000 Computer.December 1977.Retrieved15 June2009.
  6. ^"C.P.U. Basic Multiplexer Channel"(PDF).GEC 4000 Computer.December 1977.Retrieved15 June2009.
  7. ^"User Hardware Handbook – Interfaces (GEC 4080)"(PDF).GEC 4000 Computer.April 1977. pp. 4–25.Retrieved15 June2009.
  8. ^"The last of the British minis".Engineering Computing Newsletter.Retrieved7 January2017.
  9. ^"BAe Nimrod AEW 3".spyflight.co.uk.Archived fromthe originalon 2 May 2012.Retrieved17 May2009.
  10. ^abIllingworth, V. (1986). "B.001 Babbage".Dictionary of computing(2nd ed.). Oxford: Market House Books Ltd.ISBN0-19-853913-4.
  11. ^Salomon, David (February 1993). "6.1.4 BABBAGE".Assemblers and Loaders(PDF).Ellis Horwood Series In Computers And Their Applications (1 ed.). Chicester, West Sussex, UK:Ellis Horwood Limited/Simon & Schuster International Group.pp. 184–185.ISBN0-13-052564-2.Archived(PDF)from the original on 23 March 2020.Retrieved1 October2008.[1](xiv+294+4 pages)

External links[edit]

Retrieved from "https://en.wikipedia.org/w/index.php?title=GEC_4000_series&oldid=1230552380"