IBM Enterprise Systems Architecture

IBM Enterprise Systems Architectureis aninstruction set architectureintroduced by IBM as ESA/370 in 1988. It is based on theIBM System/370-XAarchitecture.

It extended the dual-address-space mechanism introduced in laterIBM System/370models by adding a new mode in which general-purpose registers 1-15 are each associated with anaccess registerreferring to an address space, with instruction operands whose address is computed with a given general-purpose register as a base register will be in the address space referred to by the corresponding address register.

The later ESA/390, introduced in 1990, added a facility to allow device descriptions to be read using channel commands and, in later models, added instructions to performIEEE 754floating-pointoperations and increased the number of floating-point registers from 4 to 16.

Enterprise Systems Architecture is essentially a32-bitarchitecture; as with System/360, System/370, and 370-XA, the general-purpose registers are 32 bits long, and the arithmetic instructions support 32-bit arithmetic. Only byte-addressable real memory (Central Storage) and Virtual Storage addressing is limited to 31 bits, as is the case with 370-XA. (IBM reserved themost significant bitto easily support applications expecting 24-bit addressing, as well as to sidestep a problem with extending two instructions to handle 32-bit unsigned addresses.) It maintains problem statebackward compatibilitydating back to 1964 with the24-bit-address/32-bit-data (System/360andSystem/370) and subsequent 24/31-bit-address/32-bit-data architecture (System/370-XA). However, the I/O subsystem is based on System/370 Extended Architecture (S/370-XA), not on the original S/370 I/O instructions.

ESA/370 architecture

ESA/370

Designer	IBM
Bits	32-bit
Introduced	1988(1988)
Design	CISC
Type	Register–Register Register–Memory Memory–Memory
Encoding	Variable(2, 4 or 6 bytes long)
Branching	Condition code,indexing, counting
Endianness	Big
Predecessor	System/370-XA
Successor	ESA/390
Registers
General-purpose	16
Floating point	4 64-bit

IBM S/370-ESA and S/390-ESA registers

General Registers 0-15 Two's complement value 0 31

Access Registers 0-15 0 0 0 0 0 0 0 P ALESN ALEN 0 6 7 8 15 16 31 ESA Access register abbreviations Bits Field Meaning 0-6 0000000 7 P Primary 0=use dispatchable-unit access list 1=use primary-space access list 8-15 ALESN access-list-entry sequence number 16-31 ALEN access-list-entry number

Control Registers0-15 See Principles of OperationorControl Registers 0 31

Floating Point Control (FPC) Register Interrupt Masks (IM) Status Flags (SF) Data Exception Code (DXC) Rounding Mode (RM) i z o u x 0 0 0 i z o u x 0 0 0 i z o u x y 0 0 0 0 0 0 0 0 RM 0 1 2 3 4 5 7 8 9 10 11 12 13 15 16 17 18 19 20 21 22 23 24 29 30 31

Floating Point Registers (hexadecimal) 0-6/0-15 S Biased exponent Mantissa 0 1 7 8 31 Mantissa (continued) 32 63

Floating Point Registers (binary, single precision) 0-15 S Biased exponent Mantissa 0 1 8 9 31

Floating Point Registers (binary, double precision) 0-15 S Biased exponent Mantissa 0 1 11 12 31 Mantissa (continued) 32 63

Enterprise Systems ArchitectureExtendedControl mode PSW 0 R 0 0 0 T I O E X Key 1 M W P AS CC Program Mask 0 0 0 0 0 0 0 0 0 1 2 4 5 6 7 8 11 12 13 14 15 16 17 18 19 20 23 24 31 A Instruction Address 32 33 63 ESA EC mode PSW abbreviations Bits Field Meaning 1 R PER Mask 5 T DAT mode 6 IO I/O Mask; subject to channel mask in CR2 7 EX External Mask; subject to external subclass mask in CR0 8-11 Key PSW key 12 E=1 ExtendedControl mode 13 M Machine-check mask 14 W Wait state 15 P Problem state 16-17 AS Address-Space Control 00=primary-space mode 01=Access-register mode 10=Secondary-space mode 11=Home-space mode 18-19 CC Condition Code 20-23 PM Program Mask Bit Meaning 20 Fixed-point overflow 21 Decimal overflow 22 Exponent underflow 23 Significance 32 A Addressing mode 0=24 bit; 1=31 bit 33-63 IA Instruction Address

On February 15, 1988, IBM announced Enterprise Systems Architecture/370 (ESA/370) for 3090 enhanced ( "E" ) models and for 4381 model groups 91E and 92E.

In addition to the primary-space and secondary-space addressing modes that later System/370 models, and System/370 Extended Architecture (S/370-XA) models, support, ESA has anaccess registermode in which each use of general register 1-15 as a base register uses an associated access register to select an address space.In addition to the normal address spaces that machines with the dual-address-space facility support, ESA also allows data spaces, which contain no executable code.

A machine may be divided into Logical Partitions (LPARs), each with its own virtual system memory so that multiple operating systems may run concurrently on one machine.

ESA/390 architecture

ESA/390

Designer	IBM
Bits	32-bit
Introduced	1990(1990)
Design	CISC
Type	Register–Register Register–Memory Memory–Memory
Encoding	Variable(2, 4 or 6 bytes long)
Branching	Condition code,indexing, counting
Endianness	Big
Predecessor	ESA/370
Successor	z/Architecture
Registers
Access 16× 32, Control 16×32, Floating Point Control (FPC) 32-bit, Prefix 32 bit, PSW 64-bit
General-purpose	16
Floating point	4 64-bit up to the G4; 16 64-bit starting with the G5

An important capability to form aParallel Sysplexwas added to the architecture in 1994.

ESA/390 also extends the Sense ID command to provide additional information about a device, and additional device-dependent channel commands, the command codes for which are provided in the Sense ID information, to allow device description information to be fetched from a device.

Starting with theSystem/390 G5,IBM introduced:

• the basic floating-point extensions facility, which increases the number of floating-point registers from 4 (0, 2, 4, 6) to 16 (0-15);
• the binary floating-point (BFP) extensions facility, which supportsIEEE 754binary floating-point numbers, with an additional floating-point control (FPC) register to support IEEE 754 modes and errors;
• the floating-point support (FPS) extensions facility, which adds instructions to load and store floating-point numbers regardless of whether they're inhexadecimalor IEEE 754 format and to convert between those formats;
• the hexadecimal floating-point (HFP) extensions facility, which adds new hexadecimal floating-point instructions corresponding to some binary floating-point instructions.

SomePC-based IBM-compatible mainframeswhich provide ESA/390 processors in smaller machines have been released over time, but are only intended for software development.

New facilities

ESA/390 adds the followingfacilities

All models

• Access-list-controlled protection

Some models

• Concurrent sense
• PER 2
• Storage-protection override
• Move-page facility 2
• Square root
• String instruction
• Suppression on protection with virtual-address enhancement
• Set address space control fast
• Subspace group
• Called-space identification
• Checksum
• Compare and move extended
• Immediate and relative instruction
• Branch and set authority
• Perform locked operation
• Additional floating-point
• Program call fast
• Resume program
• Trap
• Extended TOD clock
• TOD-clock-control override
• Store system information
• Extended translation 1
• Extended translation 2
• z/Architecture (certain instructions)
• Enhanced input/output

New channel commands

The following channel commandsare new, or have their functionality changed, in ESA/390:

ESA/390 I/O-Device Commands

Command	Bit Position
	0	1	2	3	4	5	6	7
Read configuration data	D	D	D	D	D	D	D	0
Read node identifier	D	D	D	D	D	D	D	0
Sense ID	1	1	1	0	0	1	0	0
Set interface identifier	D	D	D	D	D	D	D	1
Note: D Device dependent. The command code, if any, recognized by an I/O device may be obtained by using a sense-ID command.

References

S370-ESA

IBM Enterprise Systems Architecture/370 Principles of Operation(PDF)(First ed.). IBM. August 1988. SA22-7200-0.

S/390-ESA

IBM Enterprise Systems Architecture/390 Principles of Operation(PDF)(Ninth ed.). IBM. June 2003. SA22-7201-08.