Verilog-A

Verilog-Ais an industry standard modeling language for analog circuits. It is the continuous-time subset ofVerilog-AMS.A few commercial applications may exportMEMSdesigns in Verilog-A format.

History

Verilog-A was created to standardize theSpectrebehavioral language in the face of competition fromVHDL(an IEEE standard), which was absorbing analog capability from other languages (e.g. MAST). Open Verilog International (OVI, the body that originally standardized Verilog) agreed to support the standardization, provided that it was part of a plan to create Verilog-AMS — a single language covering both analog and digital design. Verilog-A was an all-analog subset of Verilog-AMS that was the project's first phase.

There was considerable delay (possibly procrastination) between the first Verilog-Alanguage reference manualand the fullVerilog-AMS,and in that time Verilog moved to the IEEE, leaving Verilog-AMS behind atAccellera.

The email log from AD 2000 can be foundhere.

Standard Availability

Verilog-A standard does not exist stand-alone - it is part of the complete Verilog-AMS standard. Its LRM is available at theAccellerawebsite.However, the initial and subsequent releases can be foundhere,with what will probably be the final releaseheresince future work will leverage the new net-type capabilities inSystemVerilog.Built-in types like "wreal" in Verilog-AMS will become user-defined types inSystemVerilogmore in line with theVHDLmethodology.

Compatibility with theC programming language

A subset of Verilog-A can be translated automatically to theC programming languageusing theAutomatic Device Model Synthesizer (ADMS).This feature is used for example to translate theBSIMVerilog-A transistor models, which are no more released in C, for use in simulators likengspice.

Code example

This first example gives a first demonstration of modeling in Verilog-A:

`include"constants.vams"
`include"disciplines.vams"

moduleexample(a,b,c,d,e,f);

parameterrealR=1m;
parameterrealC=1u;
parameterrealL=1u;
parameterintegergain=2;

inputa;
outputb;
inoutc,d,e,f;

electricala,b,c,d,e,f;

analogbegin

// Modelling lumped elements
//Resistor
V(c,d)<+R*I(c,d);

//Inductor
// Multiple current or voltage assignments are accumulated
V(c,d)<+L*ddt(I(c,d));

//Capacitor
I(e,f)<+C*ddt(V(e,f));

// Simple amplifier
// Voltages are referenced to ground if no second node is given
V(b)<+gain*V(a);
end
endmodule

This Verilog-AMS example implements an ideal diode, by defining the current through the branch (a,c) depending on voltage at branch terminals (a), (c), and the ambient temperature of the simulated circuit:

// Ideal Diode
modulediode(a,c);
inouta,c;
electricala,c;
parameterrealIS=1.0e-14;// User-configurable saturation current
realidio;
/*
* Calculate nonlinear current through diode depending on
* - thermal voltage $vt (at ambient temperature of simulated circuit) and
* - voltage between terminals
*/
analogbegin
idio=IS*(limexp(V(a,c)/$vt)-1);
I(a,c)<+idio;
end
endmodule

For a simple DC voltage source, the branch voltage is set to the constant (DC) value:

// DC Source
modulevsrc(p,n);
parameterrealdc=1.0;
inoutp,n;
electricalp,n;

analogbegin
// Assign constant DC voltage at each time step:
V(p,n)<+dc;
end
endmodule

A sine voltage generator can use the built-insin()function:

// A Sinusoidal Voltage Source
`include"constants.vams"

modulevsin(p,n);
parameterrealamplitude=1.0;
parameterrealfreq=50.0;
parameterrealphase=0.0;
inoutp,n;
electricalp,n;

analogbegin
V(p,n)<+amplitude*sin(`M_TWO_PI*freq*$abstime+phase);
$bound_step(0.1/freq);// demand at least 10 points per cycle to avoid aliasing issues
end
endmodule

See also

• Verilog-AMS
• Verilog

External links

• Language design objectives (circa 1994)
• Accellera Verilog Analog Mixed-Signal Group
• Language References Manuals
• The Designer's Guide to Verilog-AMS
• verilogams.com— User's manual for Verilog-AMS and Verilog-A
• Designer's Guide Community— Examples of models written in Verilog-A
• The OpenVAF compiler