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Die shrink

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Semiconductor
device
fabrication
MOSFET scaling
(process nodes)
Future

The termdie shrink(sometimesoptical shrinkorprocess shrink) refers to thescalingofmetal–oxide–semiconductor(MOS) devices. The act of shrinking adiecreates a somewhat identical circuit using a more advancedfabrication process,usually involving an advance oflithographicnodes.This reduces overall costs for a chip company, as the absence of major architectural changes to the processor lowers research and development costs while at the same time allowing more processor dies to be manufactured on the same piece ofsilicon wafer,resulting in less cost per product sold.

Die shrinks are the key to lower prices and higher performance atsemiconductor companiessuch asSamsung,Intel,TSMC,andSK Hynix,andfablessmanufacturers such asAMD(including the formerATI),NVIDIAandMediaTek.

Details

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See also:Transistor count

Examples in the 2000s include the downscaling of thePlayStation 2'sEmotion Engineprocessor fromSonyandToshiba(from180 nmCMOSin 2000 to90 nmCMOS in 2003),[1]the codenamedCedar MillPentium 4processors (from 90 nm CMOS to65 nmCMOS) andPenryn Core 2processors (from 65 nm CMOS to45 nmCMOS), the codenamedBrisbaneAthlon 64 X2processors (from90 nmSOIto65 nmSOI), various generations ofGPUsfrom both ATI and NVIDIA, and various generations ofRAMandflash memorychips from Samsung, Toshiba and SK Hynix. In January 2010, Intel releasedClarkdaleCore i5andCore i7processors fabricated with a32 nmprocess, down from a previous45 nmprocess used in older iterations of theNehalemprocessormicroarchitecture.Intel, in particular, formerly focused on leveraging die shrinks to improve product performance at a regular cadence through itsTick-Tock model.In thisbusiness model,every newmicroarchitecture(tock) is followed by a die shrink (tick) to improve performance with the same microarchitecture.[2]

Die shrinks are beneficial to end-users as shrinking a die reduces the current used by each transistor switching on or off insemiconductor deviceswhile maintaining the same clock frequency of a chip, making a product with less power consumption (and thus less heat production), increasedclock rateheadroom, and lower prices.[2]Since the cost to fabricate a 200-mm or 300-mm silicon wafer is proportional to the number of fabrication steps and not proportional to the number of chips on the wafer, die shrinks cram more chips onto each wafer, resulting in lowered manufacturing costs per chip.

Half-shrink

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In CPU fabrications, a die shrink always involves an advance to alithographicnode as defined byITRS(see list). For GPU andSoCmanufacturing, the die shrink often involves shrinking the die on a node not defined by the ITRS, for instance, the 150 nm, 110 nm, 80 nm, 55 nm, 40 nm and more currently 8 nm nodes, sometimes referred to as "half-nodes". This is a stopgap between two ITRS-definedlithographicnodes (thus called a "half-node shrink" ) before further shrink to the lower ITRS-defined nodes occurs, which helps save additional R&D cost. The choice to perform die shrinks to either full nodes or half-nodes rests with the foundry and not the integrated circuit designer.

Half-shrink
Main ITRS node Stopgap half-node
250 nm 220 nm
180 nm 150 nm
130 nm 110 nm
90 nm 80 nm
65 nm 55 nm
45 nm 40 nm
32 nm 28 nm
22 nm 20 nm
14 nm 12 nm[3]
10 nm 8 nm
7 nm 6 nm
5 nm 4 nm
3 nm —

See also

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References

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  1. ^"EMOTION ENGINE® AND GRAPHICS SYNTHESIZER USED IN THE CORE OF PLAYSTATION® BECOME ONE CHIP"(PDF).Sony.April 21, 2003.Retrieved26 June2019.
  2. ^ab"Intel's 'Tick-Tock' Seemingly Dead, Becomes 'Process-Architecture-Optimization'".Anandtech.Retrieved23 March2016.
  3. ^"Taiwan Semiconductor Mfg. Co. Ltd. Confirms" 12nm "Chip Technology Plans".The Motley Fool.RetrievedJanuary 18,2017.
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