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Back-side bus

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Inpersonal computermicroprocessorarchitecture, aback-side bus(BSB), orbackside bus,was acomputer busused on early Intel platforms to connect theCPUtoCPU cache memory,usually off-die L2. If a design utilizes a back-side bus along with afront-side bus(FSB), the design is said to use adual-bus architecture,or inIntel's terminologyDual Independent Bus(DIB)[1]architecture. The back-side bus architecture evolved when newer processors likethe second-generation Pentium IIIbegan to incorporate on-die L2 cache, which at the time was advertised asAdvanced Transfer Cache,but Intel continued to refer to the Dual Independent Bus till the end of Pentium III.[2]

History[edit]

BSB is an improvement over the older practice of using a singlesystem bus,because a single bus typically became a severebottleneckas CPUs and memory speeds increased. Due to its dedicated nature, the back-side bus can be optimized for communication with cache, thus eliminating protocol overheads and additional signals that are required on a general-purpose bus. Furthermore, since a BSB operates over a shorter distance, it can typically operate at higher clock speeds, increasing the computer's overall performance.

Cache connected with a BSB was initially external to the microprocessordie,but now is usually on-die.[3]In the latter case, the BSBclockfrequency is typically equal to the processor's,[4]and the back-side bus can also be made much wider (256-bit, 512-bit) than either off-chip or on-chip FSB.[clarification needed]

A Pentium II processor module with its cover removed showing the processor on the left and the L2 cache memory on the right

The dual-bus architecture was used in a number of designs, including theIBMandFreescale(formerly the semiconductor division ofMotorola)PowerPCprocessors (certain PowerPC604models, thePowerPC 7xxfamily,[5]and the Freescale7xxxline), as well as theIntelPentium Pro,Pentium IIand earlyPentium IIIprocessors,[6] which used it to access their L2 cache (earlier Intel processors accessed the L2 cache over the FSB, while later processors moved it on-chip).

See also[edit]

References[edit]

  1. ^"Dedicated Backside Cache Bus".PCguide. 2001-04-30.
  2. ^Pentium® III Processors for Applied Computing product brief
  3. ^"Buses: frontside and backside".ITworld.2001-04-30. Archived fromthe originalon 2001-05-02.
  4. ^"Buses: frontside and backside".ITworld.2001-04-30. Archived fromthe originalon 2001-05-02.
  5. ^"Monday a big day for Apple".CNet. 1997-11-07.
  6. ^"Backside Bus".Whatis. 2001-04-30.
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