C to HDL
C to HDLtools convertC languageorC-likecomputer codeinto ahardware description language(HDL) such asVHDLorVerilog.The converted code can then besynthesizedandtranslatedinto a hardware device such as afield-programmable gate array.Compared tosoftware,equivalent designs inhardwareconsume less power (yielding higherperformance per watt) and execute faster with lowerlatency,moreparallelismand higherthroughput.However,system designandfunctional verificationin a hardware description language can be tedious and time-consuming, so systems engineers often writecritical modulesin HDL and othermodulesin ahigh-level languageand synthesize these into HDL through C to HDL orhigh-level synthesistools.
C toRTLis another name for this methodology. RTL refers to theregister transfer levelrepresentation of a program necessary to implement it in logic.
History[edit]
Early development on C to HDL was done by Ian Page, Charles Sweeney and colleagues atOxford Universityin the 1990s who developed theHandel-Clanguage. Theycommercializedtheir research by forming Embedded Solutions Limited (ESL) in 1999 which was renamed Celoxica in September 2000. In 2008, the embedded systems departments of Celoxica was sold to Catalytic for $3 million and which later merged to become Agility Computing.[1]In January 2009,Mentor Graphicsacquired Agility's C synthesis assets.[2]Celoxica continues to trade concentrating onhardware accelerationto process transactions in the financial sector and otherindustries.[3]
Applications[edit]
C to HDL techniques are most commonly applied toapplicationsthat have unacceptably highexecution timeson existing general-purposesupercomputerarchitectures. Examples includebioinformatics,computational fluid dynamics(CFD),[clarification needed]financial processing, and oil and gas survey data analysis.Embedded applicationsrequiringhigh performanceorreal-timedata processingare also an area of use.System-on-chip(SoC) design may also take advantage of C to HDL techniques.
C-to-VHDL compilers are very useful for large designs or for implementing code that might change in the future. Designing a large application entirely in HDL may be very difficult and time-consuming; the abstraction of a high level language for such a large application will often reduce total development time. Furthermore, an application coded in HDL will almost certainly be more difficult to modify than one coded in a higher level language. If the designer needs to add new functionality to the application, adding a few lines of C code will almost always be easier than remodeling the equivalent HDL code.
Flow to HDLtools have a similar aim, but withflowrather than C-based design.
Example tools[edit]
- SmartHLS(originally LegUp), ANSI C to Verilog tool developed byMicrochip Technology,based on LLVM compiler.
- CBG CtoVA tool developed 1995-99 by DJ Greaves (University of Cambridge) that instantiated RAMs and interpreted variousSystemCconstructs and datatypes.
- C-to-Verilog tool (NISC) fromUniversity of California, Irvine
- Altium Designer 6.9 and 7.0(a.k.a. Summer 08) fromAltium
- Nios II C-to-Hardware Acceleration CompilerfromAltera
- Catapult Ctool fromMentor Graphics
- Cynthesizer fromForte Design Systems
- SystemCfromCeloxica (defunct)
- Handel-CfromCeloxica (defunct)
- DIME-CfromNallatech
- Impulse CfromImpulse Accelerated Technologies
- FpgaCwhich is an open source initiative
- SA-C programming language
- Cascade (C to RTL synthesizer) fromCriticalBlue
- Mitrion-CfromMitrionics
- SPARK (a C-to-VHDL) fromUniversity of California, San Diego[4]
- VLSI/VHDL CAD Group Index of Useful Tools fromCase Western Reserve University[5]
- MyHDLis a Python-subset compiler and simulator toVHDLandVerilog[6]
See also[edit]
- Comparison of EDA Software
- Electronic design automation(EDA)
- High-level synthesis
- Silicon compiler
- Hardware acceleration
References[edit]
- ^Clarke, Peter (1 April 2008)."Celoxica sells EDA business to Catalytic for $3 million".EE Times.
- ^Dylan McGrath (22 January 2009)."Mentor buys Agility's C synthesis assets".EETimes.
- ^Celoxica Ltd (22 January 2011)."Celoxica Ltd 'About Us'".Celoxica.Archived fromthe originalon 16 January 2011.Retrieved22 January2011.
- ^"SPARK: High-Level Synthesis using Parallelizing Compiler Techniques".Archived fromthe originalon 2009-10-24.Retrieved2020-07-11.
- ^"VLSI CAD Group Index of Useful Tools".Archived from the original on 2011-07-19.Retrieved2017-07-28.
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:CS1 maint: bot: original URL status unknown (link) - ^"Home".myhdl.org.
External links[edit]
- A good article on Dr Dobbs Journal about ImpulseC.
- An overview of flows by Daresbury Labs.[permanent dead link]
- An Overview of Hardware Compilation and the Handel-C language.
- Xilinx's ESL initiative, some products listed and C to VHDL tools.
- Altium's C-to-Hardware Compiler overview.
- Altera's Nios II C2H Acceleration Compiler White Paper.