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C to HDL

From Wikipedia, the free encyclopedia

C to HDLtools convertC languageorC-likecomputer codeinto ahardware description language(HDL) such asVHDLorVerilog.The converted code can then besynthesizedandtranslatedinto a hardware device such as afield-programmable gate array.Compared tosoftware,equivalent designs inhardwareconsume less power (yielding higherperformance per watt) and execute faster with lowerlatency,moreparallelismand higherthroughput.However,system designandfunctional verificationin a hardware description language can be tedious and time-consuming, so systems engineers often writecritical modulesin HDL and othermodulesin ahigh-level languageand synthesize these into HDL through C to HDL orhigh-level synthesistools.

C toRTLis another name for this methodology. RTL refers to theregister transfer levelrepresentation of a program necessary to implement it in logic.

History[edit]

Early development on C to HDL was done by Ian Page, Charles Sweeney and colleagues atOxford Universityin the 1990s who developed theHandel-Clanguage. Theycommercializedtheir research by forming Embedded Solutions Limited (ESL) in 1999 which was renamed Celoxica in September 2000. In 2008, the embedded systems departments of Celoxica was sold to Catalytic for $3 million and which later merged to become Agility Computing.[1]In January 2009,Mentor Graphicsacquired Agility's C synthesis assets.[2]Celoxica continues to trade concentrating onhardware accelerationto process transactions in the financial sector and otherindustries.[3]

Applications[edit]

C to HDL techniques are most commonly applied toapplicationsthat have unacceptably highexecution timeson existing general-purposesupercomputerarchitectures. Examples includebioinformatics,computational fluid dynamics(CFD),[clarification needed]financial processing, and oil and gas survey data analysis.Embedded applicationsrequiringhigh performanceorreal-timedata processingare also an area of use.System-on-chip(SoC) design may also take advantage of C to HDL techniques.

C-to-VHDL compilers are very useful for large designs or for implementing code that might change in the future. Designing a large application entirely in HDL may be very difficult and time-consuming; the abstraction of a high level language for such a large application will often reduce total development time. Furthermore, an application coded in HDL will almost certainly be more difficult to modify than one coded in a higher level language. If the designer needs to add new functionality to the application, adding a few lines of C code will almost always be easier than remodeling the equivalent HDL code.

Flow to HDLtools have a similar aim, but withflowrather than C-based design.

Example tools[edit]

See also[edit]

References[edit]

  1. ^Clarke, Peter (1 April 2008)."Celoxica sells EDA business to Catalytic for $3 million".EE Times.
  2. ^Dylan McGrath (22 January 2009)."Mentor buys Agility's C synthesis assets".EETimes.
  3. ^Celoxica Ltd (22 January 2011)."Celoxica Ltd 'About Us'".Celoxica.Archived fromthe originalon 16 January 2011.Retrieved22 January2011.
  4. ^"SPARK: High-Level Synthesis using Parallelizing Compiler Techniques".Archived fromthe originalon 2009-10-24.Retrieved2020-07-11.
  5. ^"VLSI CAD Group Index of Useful Tools".Archived from the original on 2011-07-19.Retrieved2017-07-28.{{cite web}}:CS1 maint: bot: original URL status unknown (link)
  6. ^"Home".myhdl.org.

External links[edit]