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iCE (FPGA)

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iCEis the brand name used for a family of low-powerfield-programmable gate arrays(FPGAs) produced byLattice Semiconductor.Parts in the family are marketed with the "world's smallest FPGA" tagline, and are intended for use in portable and battery-powered devices (such asmobile phones),[1]where they would be used tooffloadtasks from the device's mainprocessororsystem on chip.By doing so, the main processor and itsperipheralscan enter a low-power state or be powered off entirely, potentially increasing battery life.

Lattice acquired the iCE brand as part of its 2011 acquisition of SiliconBlue Technologies.

History

[edit]
SiliconBlue Technologies Corporation
Company typePrivate
IndustryIntegrated circuits
FoundedApril 12, 2005(2005-April-12)[2]
Founders
  • Kapil Shankar(CEO)
  • Jack Peng(CTO)
  • Andrew Chan(VP Engineering)
  • John Birkner(Product Definition)
DefunctDecember 9, 2011(2011-December-09)
FateAcquired byLattice Semiconductor
Headquarters
Santa Clara, California
,
United States[2]
ProductsFPGAs
Websitesiliconbluetech(archived copy from 2012)
A SiliconBlue FPGA ICE65 L

The iCE brand was originally used bySiliconBlue Technologies Corporation,a formerSanta Clara, California-basedfablessdesigner ofintegrated circuits.SiliconBlue was astart-upfounded in 2005 by former employees ofActel,AMD,Lattice,Monolithic Memories,andXilinx.[2][3]Most notable among the founders wasJohn Birkner,one of the inventors ofprogrammable array logic.[4]

In 2006, SiliconBlue was funded with$16 million in"Series A"capital,[5]and in June 2008 announced the iCE65 L series of devices. The devices were to befabricatedonTSMC's65 nmCMOSprocess node,which SiliconBlue claimed would provide reduced power consumption compared to contemporary FPGAs from other manufacturers.[6]In October 2008, SiliconBlue raised a further $24 million inSeries Bcapital.[5]

In 2009, the first iCE65 L devices were shipped to customers.[7]SiliconBlue also registeredSiliconBlue Technologies (Hong Kong) Limited,which remains as asubsidiaryof Lattice Semiconductor.[8][9]

In 2010, the lowest-end of the iCE65 P devices was announced by SiliconBlue. The devices were claimed to be as much as 30% faster than iCE65 L devices while maintaining similar power consumption.[10][11]In the June of the same year, SiliconBlue closed a $15 million Series C funding round.[12]

In April 2011, SiliconBlue announced that it was to release new product families, code-named "Los Angeles" and "San Francisco," using a TSMC40 nmprocess node.[13]The production of devices on a 40 nm process node was further confirmed in June 2011, when SiliconBlue received $18 million in Series D funding to bring 40 nm devices to market.[14][15]The iCE40 product family was officially released in July 2011.[16]

On 9 December 2011, SiliconBlue Technologies was acquired by Lattice Semiconductor in a $63.2 million cash buyout. As part of this buyout, Lattice received the iCE brand, manufacturing capabilities with TSMC, and a licence for various patents from Kilopass Technologies, including for its XPMone-time programmable(OTP) memory technology.[17]: 15, 8, 11 

In April 2012, Lattice announced that the iCE65 families would be discontinued.[18]The iCE40 LP and HX device families entered volume production the following month.[19]The iCE40 LP family won theElektraDigital Semiconductor Product of the Yearaward for 2012.[20]

In July 2014, the iCE40 Ultra family was announced.[21]

In February 2015, Lattice launched the iCE40 UltraLite device family. The devices in this family are claimed to operate at 30% less power than those of unspecified competitors, and are claimed to be the world's smallest FPGAs, being available in 1.4×1.4 mmpackages.[22]The family won the 2015 ElektraDigital Semiconductor Product of the Yearaward.[23]

In December 2016, Lattice launched the iCE40 UltraPlus device family. UltraPlus devices provide additional memory, additional processing elements, and support for newer interfaces and protocols compared to previous iCE40 Ultra/UltraLite devices.[24][25]

Architecture

[edit]
The architecture of iCE40 LP and HX1K devices.
See also:FPGA § Technical design,andFPGA § Architecture

iCE65 and iCE40 devices are constructed as an array ofprogrammable logic blocks(PLBs), where a PLB is a block of eightlogic cells.Each logic cell consists of a four-inputlookup table(sometimes called a 4-LUT or LUT4) with the output connected to aD flip-flop(a 1-bitstorage element). Within a PLB, each logic cell is connected to the following and preceding cell by carry logic, intended to improve the performance of constructs such asaddersandsubtractors.Interspersed with PLBs are blocks ofRAM,each fourkilobitsin size. The number of RAM blocks varies depending on the device.[26]: . 2-1 to 2-3 [27]: . 5–9 

Compared to LUT6-based architectures (such asXilinx7-series devices andAlteraStratixdevices), a LUT4-based device is unable to implement as-complexlogic functionswith the same number of logic cells. For example, a logic function with seven inputs could be implemented in eight LUT4s or two LUT6s.

iCE devices use volatileSRAMto store configuration data. As a result, the data must be loaded onto the device each time power is lost. All iCE devices support loading configuration data from aprogrammer,from an externalflash memorychip, or, with the exception of iCE40LMdevices,[28]from a so-called NVCM, or non-volatile configuration memory. The NVCM is a one-time-programmable (OTP) memory integrated into the FPGA to negate the need for an external memory chip. Lattice claims that using the NVCM can improve design security by makingreverse engineeringmore difficult.[29]

TheI/O pinson iCE devices are separated into up to four banks. On some devices each bank has its ownpower-supply pin(labelled VCCIO), allowing thelogic-highvoltage level of the I/O bank to be adjusted.[26]: 2–7 Configurable I/O voltage levels are used by iCE devices to allow support for multiple interface standards with voltage levels between 1.8 V and 3.3 V, such asLVDS.[26]: 3–1 iCE65 devices also listed being able to supportSSTLthrough this method.[27]: 11 

Development

[edit]
Main articles:Hardware description languageandDesign flow (EDA)

iCE FPGAs, as with most FPGAs andCPLDs,are typically designed for using ahardware description language(HDL), which describes an electronic circuit. Lattice iCEcube2, theIDEprovided by Lattice for developing on their FPGAs, supports theVHDLandVeriloglanguages, as well as theEDIFformat.

Open source

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The details of a specific FPGA'sbitstreamformat (which defines how the internal elements of the FPGA are connected and interact with each other) are not usually published by FPGA vendors. This means that, generally, an engineer creating a design for an FPGA must use the tools provided by the FPGA's manufacturer.

In December 2015, at32C3,[30]Project IceStorm, atoolchainconsisting ofYosys(Verilog synthesisfrontend),Arachne-pnr(place and routeand bitstream generation), andicepack(plain text-to-binary bitstream conversion) tools was presented by Claire Wolf, one of the two developers (along with Mathias Lasser) of the toolchain.[31]The toolchain is notable for being one of, if not the only, fully open-source toolchains for FPGA development. At the same December 2015 presentation, Wolf also demonstrated aRISC-VSoC design built using the open-source toolchain and running on an iCE40HX8Kdevice. As of March 2021, the toolchain supports iCE40LP/HX1K/4K/8KandUPdevices.[32]

List of iCE devices

[edit]

iCE65 (65 nm)

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TheiCE65name was used by SiliconBlue Technologies for the devices it designed for a 65 nm process node. Following the acquisition of SiliconBlue in 2011, the name was used by Lattice Semiconductor until the family was discontinued in April 2012.[18]

iCE65 L

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iCE65 Parts
Series Device LEs RAM PLLs Max. I/Os
iCE65 L L01 1280 64 kbit — 95
L04 3520 80 kbit 176
L08 7680 128 kbit 222
L16 16 896 384 kbit Un­known
iCE65 P P04 3520 80 kbit 1 174
P08 7680 128 kbit 2 Un­known
P12 12 160 160 kbit 2 Un­known

TheiCE65 Lseries of devices was intended for low-power applications and handheld devices. The series was first announced in mid 2008,[6]and first shipped to volume customers in early 2009.[7]

Information about a larger device in the series, theiCE65L16,was listed on the SiliconBlue website in 2010,[33]but no mention is made in a 2012 revision of the L-series datasheet.[27]It is unclear whether the device was ever produced commercially.

iCE65 P

[edit]

TheiCE65 P-series devices were marketed as a higher-performance version of theL-seriesdevices, intended for use in display, memory, andSERDESapplications,[34]and were announced in early 2010.[10][11]Three devices were listed as being part of the series but only one device, the lowest-endiCE65P04,was fully specified. The latest datasheet for the family, published in 2011, lists the other two parts but does not give specifications.[35]Whether these other two devices were ever commercially produced is unclear.

iCE40 (40 nm)

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Lattice uses theiCE40name for its iCE-branded devices produced on a 40 nm process node. The company has also used the codename"Los Angeles"in press releases. The iCE40 family was launched in July 2011 with iCE40 LP and HX parts,[16]and was updated in July 2014 with the iCE40 Ultra parts,[21]in February 2015 with the iCE40 UltraLite parts,[22]and in December 2016 with the iCE40 UltraPlus parts.[24]

iCE40 Ultra, UltraLite, & UltraPlus

[edit]
iCE40Ultra,UltraLite,andUltraPlusParts
Family Device LEs RAM I²C SPI DSP PWM Max. I/Os
UltraLite UL640 640 56 kbit 2 — Yes 26
UL1K 1280 56 kbit 2 Yes 26
Ultra iCE5LP1K 1100 64 kbit 1 1 2 Yes 39
iCE5LP2K 2048 80 kbit 2 2 4 Yes 39
iCE5LP4K 3520 80 kbit 2 2 4 No 39
UltraPlus UP3K 2800 1104 kbit 2 2 4 Yes 21
UP5K 5280 1144 kbit 2 2 8 Yes 39

TheiCE40 Ultra,UltraLite,andUltraPlusdevices are intended for applications with especially low limits on available space and power, such as inwearable technologyandsmart watches.[21]They are offered inchip-scale,BGA,andQFNpackages, with dimensions from 1.4×1.4 mm to 7×7 mm. All devices in family integrate one or twoI²Chard cores, withUltraandUltraPlusdevices also including hardSPIbus cores andDSPblocks.UltraLitedevices are claimed to operate at half the static current draw ofUltradevices (35 μA compared to 71 μA). Most devices in the family also include aPWMcontroller, intended to be used to driveIRorRGB LEDs.[36]: 5 

Lattice launched theUltrafamily in mid 2014,[21]and theUltraLitefamily in early 2015.[22]In 2015, theUltraLitefamily won the ElektraDigital Semiconductor Product of the Yearaward.[23]

In September 2016, theAppleiPhone 7was released and made use of an iCE5LP4K device.[37]

In December 2016, Lattice launched theUltraPlusfamily intended fordistributed processingand so-called "mobileheterogeneous computing."The devices include a 1Mbit (4×256kbit) single-port RAM (compare withdual-ported RAM), additional DSP processing elements, and support for additional interfaces, such asMIPII3C, D-PHY, and Virtual GPIO.[24][25]

iCE40 LP & LM

[edit]
iCE40LPandLMParts
Family Device LEs RAM I²C SPI PLLs Max. I/Os
LP LP384 384 No — No 39
LP640 640 32 kbit No 11
LP1K 1280 64 kbit 1 97
LP4K 3520 80 kbit 2 180
LP8K 7680 128 kbit 2 180
LM LM1K 1100 64 kbit 2 2 1 39
LM2K 2048 80 kbit 2 2 1 39
LM4K 3520 80 kbit 2 2 1 39

TheiCE40 LP(low power) andLM(low power withhard IP) parts are intended for use in battery-powered devices ashardware acceleratorsand I/Oport expanders,and for use in the same applications asiCE40 UltraandUltraLiteparts. Compared to theUltraparts,LPandLMparts are available in a wider range offootprints,offer a greater number of resources (I/O pins, embedded RAM, and logic elements), but consume more power.[28]

LPdevices differ from theUltradevices in that they do not include hard IP cores. Instead, any interface logic must be implemented in the FPGA fabric. This is generally less preferable, as so-called "soft cores" are less power-efficient than hard cores, and often are unable to operate at the samefrequencies.A soft core also reduces the number of logic cells available to the application.LMdevices integrate two I²C and two SPI hard cores, as well as two strobe generators. MostLPandLMdevices integrate one or two phase-locked loops.

The families were launched in mid 2011 and entered volume production in mid 2012.[16][19]They won the ElektraDigital Semiconductor Product of the Yearaward for 2012.[20]In 2015, it was announced thatZTEwould useLMdevices to providesensor huband infraredremote controlfunctionality in its Star 2 smartphone.[38]

iCE40 HX

[edit]
iCE40HXParts
Device LEs RAM PLLs Static current Max. I/Os
HX1K 1280 64 kbit 1 296 μA 98
HX4K 3520 80 kbit 2 1140 μA 109
HX8K 7680 128 kbit 2 1140 μA 208

TheiCE40 HXdevices are intended for high-performance applications. Compared toiCE40 LPandUltradevices, they offer lower maximumpropagation delay(7.30 nsversus 9.00–9.36 ns),[26]: 3–13, 3–15 and more I/O pins.HXseries devices consume significantly more static power and are available only in significantly larger footprints compared toUltraandLPparts (7×7 mm to 2×2 cm). Similarly to theLPdevices,HXparts do not provide hard IP cores, but do provide one or two phase-locked loops. Unlike otheriCE40devices, theHXparts are also available inQFPfootprints.[28]

TheHXparts were launched in mid 2011 alongside theLPparts,[16]and entered volume production in mid 2012.[19]

See also

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References

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  1. ^"iCE40 Ultra / UltraLite - Lattice Semiconductor".Lattice Semiconductor. Archived from the original on March 8, 2016.Retrieved5 April2016.{{cite web}}:CS1 maint: unfit URL (link)
  2. ^abcCalifornia Secretary of State Business Search,entity number C2632216.
  3. ^"SiliconBlue Team".SiliconBlue Technologies. 2006. Archived from the original on 6 December 2006.Retrieved13 May2016.{{cite web}}:CS1 maint: unfit URL (link)
  4. ^"1978: PAL User-Programmable Logic Devices Introduced".The Silicon Engine - A Timeline of Semiconductors in Computers.Computer History Museum.Archivedfrom the original on 1 April 2016.Retrieved13 May2016.
  5. ^ab"SiliconBlue Secures $24 Million in Series-B Funding"(Press release). SiliconBlue Technologies. 22 October 2008.Archivedfrom the original on 13 May 2016.Retrieved13 May2016.
  6. ^ab"SiliconBlue Pioneers New FPGA Technology for Handheld, Ultra-Low Power Applications".SiliconBlue Technologies. 2 June 2008. Archived fromthe originalon 9 April 2016.Retrieved9 April2016.
  7. ^ab"SiliconBlue announces volume production shipments of iCE65 ultra-low-power FPGAs".EETimes. 9 February 2009. Archived from the original on April 6, 2016.Retrieved6 April2016.{{cite web}}:CS1 maint: unfit URL (link)
  8. ^Company Particulars Search - ICRIS CSC Companies Registry,CR number 1330814.
  9. ^"Exhibit 21.1 - Subsidiaries of the Registrant".US Securities and Exchange Commission. 2 March 2016.Retrieved13 May2016.
  10. ^ab"SiliconBlue Enables Differentiated Mobile Broadband Products with New P-Series mobileFPGA Devices"(Press release). Reuters. 15 February 2010. Archived fromthe originalon 17 November 2010.Retrieved6 April2016.
  11. ^ab"SiliconBlue unveils new series of FPGAs targeting mobile apps".EETimes.17 February 2010.Archivedfrom the original on 13 May 2016.Retrieved13 May2016.
  12. ^"SiliconBlue Completes $15M Series C Preferred Stock Financing"(Press release). BusinessWire. 7 June 2010.Archivedfrom the original on 13 May 2016.Retrieved13 May2016.
  13. ^Clarke, Peter (5 April 2011)."SiliconBlue tips FPGA move to 40-nm".EETimes.Archivedfrom the original on 13 May 2016.Retrieved13 May2016.
  14. ^"SiliconBlue Raises $18 Million in Series D Funding"(Press release). BusinessWire. 29 June 2011.Archivedfrom the original on 7 May 2012.Retrieved13 May2016.
  15. ^Wauters, Robin (29 June 2011)."SiliconBlue Scores $18 Million in Series D Funding".TechCrunch.Archivedfrom the original on 10 March 2016.Retrieved13 May2016.
  16. ^abcdMaxfield, Clive (11 July 2011)."SiliconBlue launches 40nm mobileFPGA family (code name" Los Angeles ")".EETimes.Archivedfrom the original on 13 May 2016.Retrieved13 May2016.
  17. ^Form 10-K - Lattice Semiconductor Corporation.US Securities and Exchange Commission. 2012.
  18. ^abPCN# 08B-12: Notification of Intent to Discontinue the iCE65 Product Family.Lattice Semiconductor. 2012.
  19. ^abc"Lattice Announces Production Release Of iCE40 Los Angeles LP-Series And HX-Series mobileFPGA Device Families".Lattice Semiconductor. 8 May 2012. Archived from the original on March 31, 2016.Retrieved5 April2016.{{cite web}}:CS1 maint: unfit URL (link)
  20. ^ab"2012 Winners:: Elektra Awards".Electronics Weekly. Archived from the original on April 6, 2016.Retrieved6 April2016.{{cite web}}:CS1 maint: unfit URL (link)
  21. ^abcd"Lattice Semiconductor Launches iCE40 Ultra™ Platform for Wearable Device Development".Lattice Semiconductor. 1 December 2015. Archived from the original on March 31, 2016.Retrieved5 April2016.{{cite web}}:CS1 maint: unfit URL (link)
  22. ^abc"Lattice Semiconductor's New iCE40 UltraLite Device Enables OEMs to Accelerate Time-to-Market of Feature-Rich Mobile Devices".Lattice Semiconductor. 3 February 2015. Archived from the original on March 31, 2016.Retrieved5 April2016.{{cite web}}:CS1 maint: unfit URL (link)
  23. ^ab"2015 Winners:: Elektra Awards".Electronics Weekly. Archived from the original on April 5, 2016.Retrieved5 April2016.{{cite web}}:CS1 maint: unfit URL (link)
  24. ^abc"New iCE40 UltraPlus Devices from Lattice Semiconductor Accelerate Customer Innovation in Smartphones and IoT Edge Devices"(Press release). Lattice Semiconductor. 12 December 2016.Archivedfrom the original on 28 May 2017.Retrieved28 May2017.
  25. ^abMaxfield, Max (22 December 2016)."Lattice introduces iCE40 UltraPlus high-performance low-power FPGAs".EETimes.Archivedfrom the original on 30 January 2017.Retrieved28 May2017.
  26. ^abcdDS1040 - iCE40 LP/HX Family Data Sheet v3.2.Lattice Semiconductor. 2015.
  27. ^abciCE65™ Ultra Low-Power mobileFPGA™ Family Datasheet v2.42.Lattice Semiconductor. 2012.
  28. ^abc"iCE40 LP/HX/LM - Lattice Semiconductor".Lattice Semiconductor. Archived from the original on March 25, 2016.Retrieved6 April2016.{{cite web}}:CS1 maint: unfit URL (link)
  29. ^Lattice TN1248 - iCE40 Programming and Configuration v2.8.Lattice Semiconductor. 2015.
  30. ^"Schedule 32. Chaos Communication Congress".Chaos Computer Club. Archived from the original on January 8, 2016.Retrieved8 April2016.{{cite web}}:CS1 maint: unfit URL (link)
  31. ^Wolf, Claire; Lasser, Matthias."Project IceStorm".RetrievedMarch 6,2021.In papers and reports, please refer to Project IceStorm as follows: Claire Wolf, Mathias Lasser. Project IceStorm.
  32. ^"Project IceStorm".Claire Wolf. Archived from the original on March 6, 2021.{{cite web}}:CS1 maint: unfit URL (link)
  33. ^"SiliconBlue Technologes: iCE65 L-Series".SiliconBlue Technologies. Archived from the original on February 20, 2010.Retrieved6 April2016.{{cite web}}:CS1 maint: unfit URL (link)
  34. ^The iCE65 mobileFPGA Family Product Table v1.1.Lattice Semiconductor.
  35. ^iCE65™ P-Series Ultra Low-Power mobileFPGA™ Family v1.31.SiliconBlue Technologies. 22 April 2011.
  36. ^TN 1288 - iCE40 LED Driver Usage Guide.Lattice Semiconductor. 2014.
  37. ^"Apple iPhone 7 Teardown | Chipworks".Chipworks Inc. 15 September 2016. Archived fromthe originalon 16 September 2016.Retrieved17 September2016.
  38. ^"ZTE Chooses Lattice Semiconductor for Feature Differentiation and Integration on Star 2 Smartphone".Reuters. 23 June 2015. Archived fromthe originalon 6 April 2016.Retrieved6 April2016.
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