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LatticeMico32

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LatticeMico32
DesignerLattice Semiconductor
Bits32-bit
Introduced2006;18 years ago(2006)
DesignRISC
TypeLoad–store
EncodingFixed 32-bit
BranchingCompare and branch
EndiannessBig
ExtensionsUser-defined
OpenYes, royalty free
Registers
General-purpose32

LatticeMico32is a32-bitmicroprocessorreduced instruction set computer(RISC) soft core fromLattice Semiconductoroptimized forfield-programmable gate arrays(FPGAs). It uses aHarvard architecture,which means the instruction and data buses are separate. Bus arbitration logic can be used to combine the two buses, if desired.

LatticeMico32 is licensed under a free (IP) core license. This means that the Mico32 is not restricted to Lattice FPGAs, and can be legally used on any host architecture (FPGA,application-specific integrated circuit(ASIC), or software emulation, e.g.,QEMU). It is possible to embed a LatticeMico32 core intoXilinxandAlteraFPGAs, in addition to the Lattice Semiconductor parts the LatticeMico32 was developed for.AMD PowerTuneuses LatticeMico32.[1]

The CPU core and the developmenttoolchainare available as source-code, allowing third parties to implement changes to the processor architecture.

Features[edit]

  • RISC load/store architecture
  • 32-bit data path
  • 32-bit fixed-size instructions (all instructions are 32 bits, including jump, call and branch instructions.)
  • 32 general purpose registers (R0 is typically set to zero by convention, however R0 is a standard register and other values may be assigned to it if so desired.)
  • Up to 32 external interrupts
  • Configurable instruction set including user defined instructions
  • Optional configurable caches (direct-mapped or 2-way set-associative, with a variety of cache sizes and arrangements)
  • Optional pipelined memories
  • DualWishbonememory interfaces (one read-only instruction bus, one read-write data/peripheral bus)
  • Memory mapped I/O
  • 6 stage pipeline

Toolchain[edit]

See also[edit]

References[edit]

  1. ^"AMD x86 SMU firmware analysis".2014-12-27.

External links[edit]