Motorola 68000 series

This article is about the family of microprocessors. For the first such microprocessor in that family, seeMotorola 68000.

Motorola 68000 series

Designer	Motorola
Bits	32-bit
Introduced	1979(1979)
Design	CISC
Branching	Condition code
Endianness	Big
Registers
8 × 32-bit data registers 7 × 32-bit address registers stack pointer (address register 7) 8 × 80-bit floating-point registers if FP present

TheMotorola 68000 series(also known as680x0,m68000,m68k,or68k) is a family of32-bitcomplex instruction set computer(CISC)microprocessors.During the 1980s and early 1990s, they were popular inpersonal computersandworkstationsand were the primary competitors ofIntel'sx86microprocessors. They were best known as the processors used in the early AppleMacintosh,the SharpX68000,the CommodoreAmiga,theSinclair QL,theAtari STandFalcon,theAtari Jaguar,theSega Genesis(Mega Drive) andSega CD,thePhilips CD-i,theCapcom System I(Arcade), theAT&T UNIX PC,the TandyModel 16/16B/6000,the Sun MicrosystemsSun-1,Sun-2andSun-3,theNeXT Computer,NeXTcube,NeXTstation,andNeXTcube Turbo,earlySilicon GraphicsIRIS workstations, theAesthedes,computers fromMASSCOMP,theTexas InstrumentsTI-89/TI-92calculators, thePalm Pilot(all models running Palm OS 4.x or earlier), theControl Data CorporationCDCNETDevice Interface, theVTechPrecomputer Unlimited and theSpace Shuttle.Although no modern desktop computers are based on processors in the 680x0 series, derivative processors are still widely used inembedded systems.

Motorolaceased development of the 680x0 series architecture in 1994, replacing it with thePowerPCRISCarchitecture, which was developed in conjunction withIBMandApple Computeras part of theAIM alliance.

Family members

• Generation one (internally 16/32-bit, and produced with8-,16-,and32-bitinterfaces)
  • Motorola 68000
  • Motorola 68EC000
  • Motorola 68SEC000
  • Motorola 68HC000
  • Motorola 68008
  • Motorola 68010
  • Motorola 68012
• Generation two (internally fully 32-bit)
  • Motorola 68020
  • Motorola 68EC020
  • Motorola 68030
  • Motorola 68EC030
• Generation three (pipelined)
  • Motorola 68040
  • Motorola 68EC040
  • Motorola 68LC040
• Generation four (superscalar)
  • Motorola 68060
  • Motorola 68EC060
  • Motorola 68LC060
• Others
  • Freescale 683XX(CPU32 aka 68330, 68360 akaQUICC)
  • Freescale ColdFire
  • Freescale DragonBall
  • Philips 68070
  • APOLLO CORE 68080

Improvement history

68010:

• Virtual memory support (restartable instructions)
• 'Loop mode' for faster string and memory library primitives
• Multiply instruction uses 14 fewer clock ticks
• 2GiBdirectly accessible memory (68012variant)

68020:

• 32-bit address &arithmetic logic unit(ALU)
• Three stagepipeline
• Instructioncacheof 256 bytes
• Unrestricted word and longword data access (seealignment)
• 8×multiprocessingability
• Larger multiply (32×32 -> 64 bits) and divide (64÷32 -> 32 bits quotient and 32 bits remainder) instructions, and bit field manipulations
• Addressing modes addedscaled inde xingand another level ofindirection
• Low cost, EC = 24-bit address

68030:

• Split instruction and data cache of 256byteseach
• On-chipmemory management unit(MMU) (68851)
• Low cost EC = No MMU
• Burst Memory Interface

68040:

• Instruction and data caches of 4KBeach
• Six stage pipeline
• On-chipfloating-point unit(FPU)
• FPU lacks IEEEtranscendental functionability
• FPU emulation works with 2E71M and later chip revisions
• Low cost LC = No FPU
• Low cost EC = No FPU or MMU

68060:

• Instruction and data caches of 8 KB each
• 10 stage pipeline
• Two cycle integer multiplication unit
• Branch prediction
• Dual instruction pipeline
• Instructions in theaddress generation unit(AGU) and thereby supply the result two cycles before the ALU
• Low cost LC = No FPU
• Low cost EC = No FPU or MMU

Feature map

Year	CPU	Package	Frequency (max) [in MHz]	Address bus bits	MMU	FPU
1979	68000	64-pindual in-line package(DIP),64-pin SPDIP,68-pin PLCC,68-pin CLCC,68-pinpin grid array(PGA),64-pin QFP,68-pin QFP	8–50	24	-	-
1982	68008	48-pindual in-line package(DIP),52-pin PLCC	8–16.67	24	-	-
1982	68010	64-pin DIP,68-pin PLCC,68-pin PGA	8–16.67	24	68451	-
1982	68012	84-pin PGA	8–12.5	31	68451	-
1984	68020	114-pin PGA	12.5–33.33	32	68851	68881
-	68EC020	100-pinQuad Flat Package(QFP)	16.7–25	24	-	-
1987	68030	132-pin QFP(max33 MHz),128-pin PGA	16–50	32	MMU	68881
	68EC030	132-pin QFP,128-pin PGA	25-40	32	-	68881
1991	68040	179-pin PGA,184-pin QFP	20–40	32	MMU	FPU
	68LC040	PGA,184-pin QFP	20–33	32	MMU	-
	68EC040		20–33	32	-	-
1994	68060	206-pin PGA	50–133	32	MMU	FPU
	68LC060	206-pin PGA,208-pin QFP	50–133	32	MMU	-
	68EC060	206-pin PGA	50–133	32	-	-

Main uses

TheSega Genesisused a 68000 clocked at 7.67 MHz as its main CPU.

The 680x0 line of processors has been used in a variety of systems, from modern high-endTexas Instrumentscalculators (theTI-89,TI-92,andVoyage 200lines) to all of the members of thePalm Pilotseries that run Palm OS 1.x to 4.x (OS 5.x isARM-based), and evenradiation-hardenedversions in the critical control systems of theSpace Shuttle.

However, the 680x0 CPU family became most well known as the processors powering advanceddesktop computersandvideo game consolessuch as the AppleMacintosh,the CommodoreAmiga,theSinclair QL,theAtari ST,the SNKNG AES/Neo Geo CD,Atari Jaguar,Commodore CDTV,and several others. The 680x0 were also the processors of choice in the 1980s forUnixworkstationsandserverssuch as AT&T'sUNIX PC,Tandy'sModel 16/16B/6000,Sun Microsystems'Sun-1,Sun-2,Sun-3,NeXT Computer,Silicon Graphics(SGI), and numerous others. There was a 68000 version ofCP/Mcalled CP/M-68K, which was initially proposed to be the Atari ST operating system, but Atari choseAtari TOSinstead. Many system specific ports of CP/M-68K were available, for example, TriSoft offered a port of the CP/M-68K for the Tandy Model 16/16B/6000.

Also, and perhaps most significantly, the first several versions of Adobe'sPostScriptinterpreters were 68000-based. The 68000 in the AppleLaserWriterand LaserWriter Plus was clocked faster than the version used then in Macintosh computers. A fast 68030 in later PostScript interpreters, including the standard resolution LaserWriter IIntx, IIf and IIg (also 300 dpi), the higher resolution LaserWriter Pro 600 series (usually 600 dpi, but limited to 300 dpi with minimum RAM installed) and the very high resolutionLinotronicimagesetters, the 200PS (1500+ dpi) and 300PS (2500+ dpi). Thereafter, Adobe generally preferred a RISC for its processor, as its competitors, with their PostScript clones, had already gone with RISCs, often an AMD 29000-series. The early 68000-based Adobe PostScript interpreters and their hardware were named forCold War-era U.S. rockets and missiles: Atlas, Redstone, etc.

Today, these systems are either end-of-line (in the case of the Atari), or are using different processors (in the case of Macintosh, Amiga, Sun, and SGI). Since these platforms had their peak market share in the 1980s, their original manufacturers either no longer support an operating system for this hardware or are out of business. However, theLinuxandNetBSDoperating systems still include support for 68000 processors.

The 68000 processors were also used in theSega Genesis(Mega Drive) andSNKNeo Geoconsoles as the main CPU. Other consoles such as theSega Saturnused the 68000 for audio processing and other I/O tasks, while theAtari Jaguarincluded a 68000 which was intended for basic system control and input processing, but due to the Jaguar's unusual assortment of heterogeneous processors was also frequently used for running game logic. Many arcade boards also used 68000 processors including boards from Capcom, SNK, and Sega.

Microcontrollersderived from the 68000 family have been used in a huge variety of applications. For example,CPU32andColdFiremicrocontrollers have been manufactured in the millions as automotive engine controllers.

Many proprietary video editing systems used 68000 processors, such as the MacroSystem Casablanca, which was a black box with an easy to use graphic interface (1997). It was intended for the amateur and hobby videographer market. It is also worth noting its earlier, bigger and more professional counterpart, the "DraCo" (1995). The groundbreakingQuantel Paintboxseries of early based 24-bit paint and effects system was originally released in 1981 and during its lifetime it used nearly the entire range of 68000 family processors, with the sole exception of the 68060, which was never implemented in its design. Another contender in the video arena, the Abekas 8150 DVE system, used the 680EC30, and the Play Trinity, later renamed Globecaster, uses several 68030s. The Bosch FGS-4000/4500 Video Graphics System manufactured by Robert Bosch Corporation, later BTS (1983), used a 68000 as its main processor; it drove several others to perform 3D animation in a computer that could easily apply Gouraud and Phong shading. It ran a modifiedMotorola VERSAdosoperating system.

Architecture

Motorola 68000 series registers

31 ... 23 ... 15 ... 07 ... 00 (bit position) Data registers D0 Data 0 D1 Data 1 D2 Data 2 D3 Data 3 D4 Data 4 D5 Data 5 D6 Data 6 D7 Data 7 Address registers A0 Address 0 A1 Address 1 A2 Address 2 A3 Address 3 A4 Address 4 A5 Address 5 A6 Address 6 Stack pointers A7 / USP Stack Pointer (user) A7' / SSP Stack Pointer (supervisor) Program counter PC Program Counter

Status Register 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 (bit position) T S M 0 I 0 0 0 X N Z V C SR

People who are familiar with thePDP-11orVAXusually feel comfortable with the 68000 series. With the exception of the split of general-purpose registers into specialized data and address registers, the 68000 architecture is in many ways a 32-bit PDP-11.

It had a moreorthogonal instruction setthan those of many processors that came before (e.g., 8080) and after (e.g., x86). That is, it was typically possible to combine operations freely with operands, rather than being restricted to using certain addressing modes with certain instructions. This property made programming relatively easy for humans, and also made it easier to write code generators for compilers.

The 68000 series has eight 32-bit general-purpose dataregisters(D0-D7), and eight address registers (A0-A7). The last address register is thestack pointer,and assemblers accept the label SP as equivalent to A7.

In addition, it has a 16-bit status register. The upper 8 bits is the system byte, and modification of it is privileged. The lower 8 bits is the user byte, also known as the condition code register (CCR), and modification of it is not privileged. The 68000 comparison, arithmetic, and logic operations modify condition codes to record their results for use by later conditional jumps. The condition code bits are "zero" (Z), "carry" (C), "overflow" (V), "extend" (X), and "negative" (N). The "extend" (X) flag deserves special mention, because it is separate from thecarry flag.This permits the extra bit from arithmetic, logic, and shift operations to be separated from the carry for flow-of-control and linkage.

While the 68000 had a 'supervisor mode', it did not meet thePopek and Goldberg virtualization requirementsdue to the single instruction 'MOVE from SR', which copies the status register to another register, being unprivileged but sensitive. In theMotorola 68010and later, this was made privileged, to better support virtualization software.

The 68000 seriesinstruction setcan be divided into the following broad categories:

• Load and store (MOVE)
• Arithmetic(ADD, SUB, MULS, MULU, DIVS, DIVU)
• Bit shifting(ASL, ASR, LSL, LSR)
• Bit rotation (ROR, ROL, ROXL, ROXR)
• Logic operations(AND, OR, NOT, EOR)
• Type conversion (bytetowordandvice versa)
• Conditionalandunconditional branches(BRA, Bcc - BEQ, BNE, BHI, BLO, BMI, BPL, etc.)
• Subroutineinvocation and return (BSR, RTS)
• Stackmanagement (LINK, UNLK, PEA)
• Causing and responding tointerrupts
• Exception handling
• There is no equivalent to the x86CPUIDinstruction to determine what CPU or MMU or FPU is present.

TheMotorola 68020added some new instructions that include some minor improvements and extensions to the supervisor state, several instructions for software management of a multiprocessing system (which were removed in the 68060), some support for high-level languages which did not get used much (and was removed from future 680x0 processors), bigger multiply (32×32→64 bits) and divide (64÷32→32 bits quotient and 32 bits remainder) instructions, and bit field manipulations.

The standardaddressing modesare:

• Register direct
  • Data register, e.g. "D0"
  • Address register, e.g. "A0"
• Register indirect
  • Simple address, e.g. (A0)
  • Address with post-increment, e.g. (A0)+
  • Address with pre-decrement, e.g. −(A0)
  • Address with a 16-bit signed offset, e.g. 16(A0)
  • Register indirect with index register and 8-bit signed offset e.g. 8(A0,D0) or 8(A0,A1)

  For (A0)+ and −(A0), the actual increment or decrement value is dependent on the operand size: a byte access adjusts the address register by 1, a word by 2, and a long by 4.

• PC (program counter) relative with displacement
  • Relative 16-bit signed offset, e.g. 16(PC). This mode was very useful for position-independent code.
  • Relative with 8-bit signed offset with index, e.g. 8(PC,D2)
• Absolute memory location
  • Either a number, e.g. "$4000", or a symbolic name translated by the assembler
  • Most assemblers used the "$" symbol forhexadecimal,instead of "0x" or a trailing H.
  • There were 16 and 32-bit versions of this addressing mode
• Immediate mode
  • Data stored in the instruction, e.g. "#400"
• Quick immediate mode
  • 3-bit unsigned (or 8-bit signed with moveq) with value stored in opcode
  • In addq and subq, 0 is the equivalent to 8
  • e.g. moveq #0,d0 was quicker than clr.l d0 (though both made D0 equal to 0)

Plus: access to thestatus register,and, in later models, other special registers.

The Motorola 68020 added ascaled inde xingaddress mode, and added another level ofindirectionto many of the pre-existing modes.

Most instructions have dot-letter suffixes, permitting operations to occur on 8-bit bytes ( ".b" ), 16-bit words ( ".w" ), and 32-bit longs ( ".l" ).

Most instructions aredyadic,that is, the operation has a source, and a destination, and the destination is changed. Notable instructions were:

• Arithmetic: ADD, SUB, MULU (unsigned multiply), MULS (signed multiply), DIVU, DIVS, NEG (additive negation), and CMP (a comparison done by subtracting the arguments without storing the result, setting the status bits)
• Binary-coded decimalarithmetic: ABCD, NBCD, and SBCD
• Logic: EOR (exclusive or), AND, NOT (logical not), OR (inclusive or)
• Shifting: (logical, i.e. right shifts put zero in the most-significant bit) LSL, LSR, (arithmetic shifts,i.e. sign-extend the most-significant bit) ASR, ASL, (rotates through eXtend and not) ROXL, ROXR, ROL, ROR
• Bit test and manipulationin memory or data register: BSET (set to 1), BCLR (clear to 0), BCHG (invert) and BTST (no change). All of these instructions first test the destination bit and set (clear) the CCR Z bit if the destination bit is 0 (1), respectively.
• Multiprocessingcontrol: TAS,test-and-set,performed an indivisible bus operation, permittingsemaphoresto be used to synchronize several processors sharing a single memory
• Flow of control: JMP (jump), JSR (jump to subroutine), BSR (relative address jump to subroutine), RTS (return fromsubroutine), RTE (return fromexception,i.e. an interrupt), TRAP (trigger a software exception similar to software interrupt), CHK (a conditional software exception)
• Branch: Bcc (where the "cc" specified one of 14 tests of the condition codes in the status register: equal, greater than, less-than, carry, and most combinations and logical inversions, available from the status register). Of the remaining two possible conditions, always true and always false, BRA (branch always) has a separate mnemonic, and BSR (branch to subroutine) takes the encoding that would otherwise have been 'branch never'.
• Decrement-and-branch: DBcc (where "cc" was as for the branch instructions), which, provided the condition wasfalse,decremented the low word of a D-register and, if the result was not -1 ($FFFF), branched to a destination. This use of −1 instead of 0 as the terminating value allowed the easy coding of loops that had to do nothing if the count was 0 to start with, with no need for another check before entering the loop. This also facilitated nesting of DBcc.

68050 and 68070

Motorola mainly used even numbers for major revisions to the CPU core such as 68000, 68020, 68040 and 68060. The 68010 was a revised version of the 68000 with minor modifications to the core, and likewise the 68030 was a revised 68020 with some more powerful features, none of them significant enough to classify as a major upgrade to the core.

There was no 68050, though at one point it was a project within Motorola. Odd-numbered releases had always been reactions to issues raised within the prior even numbered part; hence, it was generally expected that the 68050 would have reduced the 68040's power consumption (and thus heat dissipation), improved exception handling in the FPU, used a smaller feature size and optimized the microcode in line with program use of instructions. Many of these optimizations were included with the 68060 and were part of its design goals. For any number of reasons, likely that the 68060 was in development, that the Intel 80486 was not progressing as quickly as Motorola assumed it would, and that 68060 was a demanding project, the 68050 was cancelled early in development.

There is also no revision of the68060,as Motorola was in the process of shifting away from the 68000 and88kprocessor lines into its newPowerPCbusiness, so the 68070 was never developed. Had it been, it would have been a revised 68060, likely with a superior FPU (pipelining was widely speculated upon on Usenet).

There was a CPU with the68070designation, which was a licensed and somewhat slower version of the 16/32-bit 68000 with a basic DMA controller,I²Chost and an on-chip serial port. This 68070 was used as the main CPU in thePhilipsCD-i.This CPU was, however, produced byPhilipsand not officially part of Motorola's 680x0 lineup.

Last generation

The 4th-generation68060provided equivalent functionality (though not instruction-set-architecture compatibility) to most of the features of the IntelP5 microarchitecture.

Other variants

The Personal ComputersXT/370andAT/370PC-based IBM-compatible mainframeseach included two modified Motorola 68000 processors with custommicrocodeto emulateS/370mainframe instructions.

An Arizona-based company,Edge Computer Corp,reportedly founded by former Honeywell designers, produced processors compatible with the 68000 series, these being claimed as having "a three to five times performance – and18 to 24 months’ time– advantage "over Motorola's own products.In 1987, the company introduced the Edge 1000 range of "32-bit superminicomputers implementing the Motorola instruction set in the Edge mainframe architecture", employing two independent pipelines - an instruction fetch pipeline (IFP) and operand executive pipeline (OEP) - relying on a branch prediction unit featuring a 4096-entry branch cache, retrieving instructions and operands over multiple buses.An agreement between Edge Computer and Olivetti subsequently led to the latter introducing products in its own "Linea Duo" range based on Edge Computer's machines.The company was subsequently renamed to Edgcore Technology Inc.(also reported as Edgecore Technology Inc.). Edgcore's deal withOlivettiin 1987 to supply the company's E1000 processor was followed in 1989 by another deal withPhilips Telecommunications Data Systemsto supply the E2000 processor, this supporting the 68030 instruction set and reportedly offering a performance rating of 16 VAX MIPS.Similar deals withNixdorf ComputerandHitachiwere also signed in 1989.

Edge Computer reportedly had an agreement with Motorola.Despite increasing competition from RISC products, Edgcore sought to distinguish its products in the market by emphasising its "alliance" with Motorola, employing a marketing campaign drawing from Aesop's fables with "the fox (Edgecore) who climbs on the back of the stallion (Motorola) to pluck fruit off the higher branches of the tree".Other folktale advertising themes such asLittle Red Riding Hoodwere employed.With the company's investors having declined to finance the company further, and with a number of companies having been involved in discussions with other parties,Arix Corp.announced the acquisition of Edgcore in July 1989.Arix was reportedly able to renew its deal with Hitachi in 1990, whereas the future of previous deals with Olivetti and Philips remained in some doubt after the acquisition of Edgcore.

In 1992, a company calledInternational Meta Systems(IMS) announced a RISC-based CPU, theIMS 3250,that could reportedly emulate the "Intel 486 or Motorola 68040 at full native speeds and at a fraction of their cost". Clocked at100MHz,emulations had supposedly been developed of a25 MHz486 and30 MHz68040, including floating-point unit support, with the product aiming for mid-1993 production at a per-unit cost of$50 to 60.Amidst the apparent proliferation of emulation support in processors such as thePowerPC 615,in 1994, IMS had reportedly filed a patent on its emulation technology but had not found any licensees.Repeated delays to the introduction of this product, blamed on one occasion on "a need to improve the chip's speech-processing capabilities",apparently led to the company seeking to introduce another chip, theMeta6000,aiming to compete with Intel's P6 products.Ultimately, IMS entered bankruptcy having sold patents to a litigator, TechSearch, who in 1998 attempted to sue Intel for infringement of an IMS patent.TechSearch reportedly lost their case but sought to appeal, also seeking to sue Intel for "libel and slander" on the basis of comments made by an Intel representative who had characterised TechSearch's business model unfavourably in remarks to the press.

After the mainline 68000 processors' demise, the 68000 family has been used to some extent inmicrocontrollerand embedded microprocessor versions. These chips include the ones listed under "other" above, i.e. theCPU32(aka68330), theColdFire,theQUICCand theDragonBall.

With the advent ofFPGAtechnology an international team of hardware developers have re-created the68000with many enhancements as an FPGA core. Their core is known as the68080and is used in Vampire-branded Amiga accelerators.

Magnetic Scrollsused a subset of the 68000's instructions as a base for the virtual machine in theirtext adventures.

Competitors

Desktop

During the 1980s and early 1990s, when the 68000 was widely used in desktop computers, it mainly competed againstIntel'sx86architecture used inIBM PC compatibles.Generation 1 68000 CPUs competed against mainly the16-bit8086,8088,and80286.Generation 2 competed against the80386(the first 32-bit x86 processor), and generation 3 against the80486.The fourth generation competed with theP5Pentiumline, but it was not nearly as widely used as its predecessors, since much of the old 68000 marketplace was either defunct or nearly so (as was the case with Atari and NeXT), or converting to newer architectures (PowerPCfor theMacintoshandAmiga,SPARCforSun,andMIPSforSilicon Graphics(SGI)).

Embedded

Main article:Microcontroller § Types

There are dozens of processor architectures that are successful inembedded systems.Some are microcontrollers which are much simpler, smaller, and cheaper than the 68000, while others are relatively sophisticated and can run complex software. Embedded versions of the 68000 often compete with processor architectures based onPowerPC,ARM,MIPS,SuperH,and others.

See also

• VMEbus,an externalcomputer bus standarddesigned for the 68000 series

Bibliography

• Howe, Dennis, ed. (1983).Free On-Line Dictionary of Computing.Imperial College, London.http://foldoc.org.Retrieved September 4, 2007.

External links

• BYTE Magazine, September 1986: The 68000 Family
• A quite an extensive list of operating systems supporting 680x0 processors