Open Verification Methodology

TheOpen Verification Methodology(OVM) is a documentedmethodologywith a supporting building-block library for the verification of semiconductor chip designs. The initial version, OVM 1.0, was released in January, 2008,^[1]and regular updates have expanded its functionality. The latest version is OVM 2.1.2, released in January, 2011.

The reuse concepts within the OVM were derived mainly from the Universal Reuse Methodology (URM) which was, to a large part, based on thee Reuse Methodology(ERM) for thee Verification Languagedeveloped by Verisity Design in 2001. The OVM also brings in concepts from the Advanced Verification Methodology (AVM). TheUVMclass library brings much automation to theSystemVeriloglanguage such as sequences and data automation features (packing, copy, compare, etc.). The UVM also has recommendations for code packaging and naming conventions.

References

^OVM 1.0 Announcement

External links

EDA Playground- run OVM simulations from a web browser (free online IDE)
OVM Relationship to the UVM

[1] OVM 1.0 Announcement

[1]