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WDC 65C816

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WDC 65C816
PDIP40 package
General information
Launched1985;39 years ago(1985)
Common manufacturer
Performance
Max.CPUclock rate1 MHz to 14 MHz
Data width
  • 8 (external)
  • 16 (internal)
Address width24 bits
Architecture and classification
Instruction set6502
Number of instructions92
Physical specifications
Packages
Products, models, variants
Variant
    • W65C802 (pin-compatible with W65C02)
    • W65C265 (MCU)
History
Predecessors
SuccessorWDC 65C832[1][2][3](never released)

TheW65C816S(also65C816or65816) is a 16-bitmicroprocessor(MPU) developed and sold by theWestern Design Center(WDC). Introduced in 1983,[4]the W65C816S is an enhanced version of theWDC 65C028-bitMPU, itself aCMOSenhancement of the venerableMOS Technology6502NMOSMPU. The 65C816 is the CPU for theApple IIGSand, in modified form, theSuper Nintendo Entertainment System.

The65in the part's designation comes from its 65C02 compatibility mode, and the816signifies that the MPU has selectable 8- and16-bitregistersizes. In addition to the availability of 16-bit registers, the W65C816S extendsmemory addressingto24 bits,supporting up to 16megabytesofrandom-access memory.It has an enhanced instruction set and a 16-bitstack pointer,as well as several new electrical signals for improved system hardware management.

Atreset,the W65C816S starts in "emulation mode", meaning it substantially behaves as a 65C02. Thereafter, the W65C816S may be switched to "native mode" with a two instruction sequence, causing it to enable all enhanced features, yet still maintain a substantial degree ofbackward compatibilitywith most 65C02 software. However, unlike thePDIP40version of the 65C02, which is apin-compatiblereplacement for its NMOS ancestor, the PDIP40 W65C816S is not pin-compatible with any other 6502 family MPU.

TheW65C802or65802is completely software-compatible with the 65C816, but is electrically-compatible with the 6502 and 65C02. Hence the 65C802 could be used as a drop-in replacement in most systems equipped with a 6502 or 65C02. However, the 65C802 cannot emit a 24-bit address, which limits it to a 64 KB address space. The 65C802 is no longer produced.

History

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PLCC-44version ofW65C816Smicroprocessor, shown mounted on asingle-board computer.

In 1981,Bill Mensch,founder andCEOof WDC, began development of the 65C02 with his production partners, primarilyRockwell SemiconductorandSynertek.The primary goal of the 65C02 effort was to move from the original 6502's NMOS process to the CMOS process, which would allow it to run at much lower power levels, somewhere between1⁄10and1⁄20at any given clock speed. Also desired was the ability to raise the maximum supported clock speed. The 65C02 design addressed chip errata present in the NMOS 6502 (e.g., the infamousJMP (<addr>)bug) and introduced new instructions and new addressing modes for some existing instructions.[5]

Development of the W65C816S commenced in 1982 after Mensch consulted withApple Computeron a new version of theApple IIseries ofpersonal computersthat would, among other things, have improved graphics and sound. Apple wanted an MPU that would be software compatible with the 6502 then in use in the Apple II but with the ability to address more memory, and to load and store 16 bit words. The result was the 65C816, finished in March 1984, with samples provided to both Apple andAtariin the second half of the year and full release in 1985.[6]Mensch was aided during the design process by his sister Kathryn, who was responsible for part of the device's layout.

The same process also led to the 65C802, which was identical inside to the 65C816. Both were produced on the same fabrication lines and diverged only during the last metalization stages when the chip was being connected to the external pins. In the 65C802, those pins had the same layout as the original 6502, which allowed it to be used as a drop-in replacement while still allowing the 16-bit processing of the CPU to be used. However, as it used the original pinout it had only 16 addressing pins, and could therefore only access 64 KB of external memory.[7]Typically, when hardware manufacturers designed a project from the ground up, they used the 65C816 rather than the 65C802, resulting in the latter being withdrawn from production.

Apple subsequently integrated the 65C816 into theApple IIGScomputer. The basic 65C816 design wassecond-sourcedbyVLSI Technology,[8]GTE,Sanyoand others from the mid-to-late 1980s to the early 1990s.

In the 1990s, both the 65C816 and 65C02 were converted to a fullystatic core,which made it possible to completely stop theprocessor's Ø2 clockwithout loss of register contents. This feature, along with the use ofasynchronous static RAM,made it possible to produce designs that used minimal power when in a standby state.

As of April 2024,the W65C816S is available from WDC in 40 pinPDIP,PLCC44,or 44-pinTQFPpackaging, as anMCUthrough the W65C265,[9]and as IP cores forASICintegration[10][11](for exampleWinbond's W55V9x series of TVEdutainmentICs[12]).

W65C802P

Features

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WDC 65c816 registers
23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 (bit position)
Main registers
B A accumulators(CCombined)
Index registers
X Xindex
Y Yindex
0 0 0 0 0 0 0 0 DP DirectPage pointer
0 0 0 0 0 0 0 0 SP StackPointer
DB 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DataBank register
PB PC ProgramBank:ProgramCounter
Status register
n v m x d i z c Program status register
e Program status registermode flag

WDC 65c816 features:

  • Fully staticCMOSdesign offers low power consumption (300µAat 1MHz) and increased noise immunity.
  • Wide operatingvoltagerange: 1.8 V to 5.0 V ± 5%.
  • Wideoperating frequencyrange, officially 14 MHz maximum at 5 volts (20Mhz inSuperCPU), using a single-phase clock source.
  • Emulation mode allows substantial software compatibility with the NMOS 6502 and CMOS 65C02, excepting undocumentedopcodes.All 256 opcodes in the 65C816 are functional in both operating modes.
  • 24-bit memory addressing provides access to 16 MB ofmemory space.
  • 16-bitALU,accumulator(C),stack pointer(SP), andindex registers(XandY).
  • 16-bit direct page (aka zero page) register (DP).
  • 8-bit data bank (DB) and program bank (PB) registers, generating bits 16–23 of 24-bit code and data addresses. Separate program and data bank registers allow programsegmentationand 16 MB linear data addressing.
  • Valid data address (VDA) and valid program address (VPA) control outputs for memory qualification, dualcacheand cycle stealDMAimplementation.
  • Vector pull (VPB) control output to indicate when aninterrupt vectoris being fetched.
  • Abort (ABORTB) input and associated vector supports processor repairs of bus error conditions, such aspage faultsand memory access violations.
  • Direct page register and stack relative addressing provides capability forreentrant,recursiveandre-locatableprogramming.
  • 24addressing modes—13 original 6502 modes with 92instructionsusing 256op codes,including most new opcodes implemented in the 65C02.
  • Block-copy instructions (MVNandMVP), allowing rapid copying of data structures from one area ofRAMto another with minimal code.
  • Wait-for-Interrupt (WAI) and Stop-the-Clock (STP) instructions furtherreduce power consumption,decreaseinterrupt latencyand allow synchronization with external events.
  • Co-Processor(COP) instruction with associated vector supports co-processor configurations, e.g.,floating point processors.
  • Reserved "escape" (WDM) instruction for future two-byte opcodes and a link to future designs (WDM are the initials of W65C816S designerWilliam D. Mensch).

Comparison with earlier models

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Two modes

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The 65C816 has two operating modes: "emulation mode", in which the 16-bit operations are invisible—the index registers are forced to eight bits—and the chip appears to be very similar to the 6502, with the same cycle timings for the opcodes; and "native mode", which exposes all new features. The CPU automatically enters emulation mode when it is powered on or reset, which allows it to replace a 65(C)02, assuming one makes the required circuit changes to accommodate the different pin layout.[5]

16-bit registers

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The most obvious change to the 65C816 when running in native mode is the expansion of the various registers from 8-bit to 16-bit sizes. This enhancement affects the accumulator (A), theXandYindex registers,and thestack pointer(SP). It does not affect theprogram counter(PC), which has always been 16-bit.[13]

When running in native mode, two bits in the status register change their meaning. In the original 6502, bits 4 and 5 were not used, although bit 4 is referred to as the break (b) flag. In native mode, bit 4 becomes thexflag and bit 5 becomes themflag. These bits control whether or not theindex registers(x) and accumulator/memory (m) are 8-bit or 16-bit in size. Zeros in these bits set 16-bit sizes, ones set 8-bit sizes. These bits are locked at ones when the processor is powered on or reset, but become changeable when the processor is switched to native mode.[13]

In native mode operation, the accumulator and index registers may be set to 16- or 8-bit sizes at the programmer’s discretion by using theREPandSEPinstructions to manipulate themandxstatus register bits. This feature gives the programmer the ability to perform operations on either word- and byte-size data. As the accumulator and index register sizes are independently settable, it is possible, for example, to have the accumulator set to eight bits and the index registers set to 16 bits, giving the programmer the ability to manipulate individual bytes over a 64KB range without having to perform pointer arithmetic.

When register sizes are set to 16 bits, a memory access will fetch or store two contiguous bytes at the rate of one byte per clock cycle. Hence a read-modify-write instruction, such asROR <addr>,when used while the accumulator is set to 16 bits, will affect two contiguous bytes of memory, not one and will consume more clock cycles than when the accumulator is set to eight bits. Similarly, all arithmetic and logical operations will be 16-bit operations.[14]

24-bit addressing

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The other major change to the system while running in native mode is that the memory model is expanded to a 24-bit format from the original 16-bit format of the 6502. The 65c816 makes use of two 8-bit registers, the data bank register (DB) and the program bank register (PB), to set bits 16-23 of the address, effectively generating 24-bit addresses. In both cases, 'bank' refers to a contiguous 64 KB segment of memory that is bounded by the address range$xx0000-$xxFFFF,wherexxis the bank address, that is, bits 16-23 of the effective address. BothDBandPBare initialized to$00at power-on or reset.[15]

During anopcodeoroperandfetch cycle,PBis prepended to theprogram counter(PC) to form the 24-bit effective address. ShouldPC"wrap" (return to zero),PBwill not be incremented. Hence a program is bounded by the limits of the bank in which it is executing. Implied by this memory model is that branch and subroutine targets must be in the same bank as the instruction making the branch or call, unless "long" jumps or subroutine calls are used to execute code in another bank. There is no programmatic means by whichPBcan be directly changed.[16]

During a data fetch or store cycle,DBis prepended to a 16-bit data address to form the 24-bit effective address at which data will be accessed. This processor characteristic makes it possible to sanely execute 6502 or 65c02 code that uses 16-bit addresses to reference data elements. UnlikePB,DBcan be changed under program control, something that might be done to access data beyond the limits of 16-bit addressing. Also,DBwill temporarily increment if an address is indexed beyond the limits of the bank currently inDB.DBis ignored if a 24-bit address is specified as the operand to a data fetch/store instruction, or if the effective address is on direct (zero) page or thehardware stack.In the latter case, an implied bank$00is used to generate the effective address.[17]

A further addition to the register set is the 16-bit direct page register (DP), which sets the base address for what was formerly called thezero page,but now referred to asdirect page.Direct page addressing uses an 8-bit address, which results in faster access than when a 16- or 24-bit address is used. Also, some addressing modes that offer indirection are only possible on direct page. In the 65(c)02, the direct page is always the first 256 bytes of memory, hence “zero page”. In native mode, the 65c816 can relocate direct (zero) page anywhere in bank$00(the first 64 KB of memory) by writing the 16-bit starting address intoDP.There is a one-cycle access penalty ifDPis not set to an exact page boundary, that is, if the value inDPis not$xx00,wherexxis the most-significant byte.[18]

Switching between modes

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The current mode of operation is stored in the emulation (e) bit. Having already added the newxandmbits to the previous set of six flags in the status register (SR), there were not enough bits left to hold the new mode bit. Instead, a unique solution was used in which the mode bit was left "invisible", unable to be directly accessed. TheXCE(eXchangeCarry withEmulation) instruction exchanges the value of the emulation bit with the carry (c) bit, bit 0 inSR.For instance, if one wants to enter native mode after the processor has started up, one would useCLCto clear the carry bit, and thenXCEto write it to the emulation bit.[19]Returning to 65c02 emulation mode usesSECfollowed byXCE.[20]

Internally, the 65c816 is a fully 16-bit design. Themandxbits inSRdetermine how the user registers (accumulator and index) appear to the rest of the system. Upon reset, the 65c816 starts in 6502 emulation mode, in whichmandxare locked to1.Hence the registers are locked to eight-bit size. The most significant byte (MSB) of the accumulator (theB-accumulator) is not directly accessible but can be swapped with the least significant byte (LSB) of the accumulator (theA-accumulator) by using theXBAinstruction. There is no corresponding operation for the index registers (XandY), whose MSBs are locked at$00.

Upon being switched to native mode, the MSB ofXandYwill be zero, and theB-accumulator will be unchanged. If thembit inSRis cleared, theB-accumulator will be "ganged" to theA-accumulator to form a 16-bit register (called theC-accumulator). A load/store or arithmetic/logical operation involving the accumulator or memory will be a 16-bit operation—two bus cycles are required to fetch/store a 16-bit value.

If thexbit inSRis cleared, both index registers will be set to 16 bits. If used to index an address, e.g.,LDA SOMEWHERE,X,the 16-bit value in the index register will be added to the base address to form the effective address.

If thembit inSRis set, the accumulator will return to being an 8-bit register and subsequent operations on the accumulator, with a few exceptions, will be 8-bit operations. TheB-accumulator will retain the value it had when the accumulator was set to 16 bits. The exceptions are the instructions that transfer the direct page register (DP) and stack pointer (SP) to/from the accumulator. These operations are always 16 bits wide in native mode, regardless of the condition of thembit inSR.

If thexbit inSRis set, not only will the index registers return to being 8 bits, whatever was in the MSB while they were 16 bits wide will be lost, something an assembly language programmer cannot afford to forget.[21]

Applications

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Systems based on 65c816 variants:

See also

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References

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Citations

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  1. ^Mensch, William D."A Report on the 65c832".Archivedfrom the original on 7 Apr 2024.Retrieved7 Apr2024.
  2. ^"W65C832 Information, Specification, and Data Sheet (March 1990)"(PDF).ReActive Micro.6 Sep 2010 [Mar 1990].Archived(PDF)from the original on 7 Apr 2024.Retrieved7 Apr2024.
  3. ^"W65C832 Information, Specification, and Data Sheet"(PDF).6502.org.Archived fromthe original(PDF)on 30 Jun 2023.Retrieved7 Apr2024.
  4. ^Chronology of Microprocessors (1980–1989)
  5. ^abEyes & Lichty 1986,p. 42.
  6. ^Eyes & Lichty 1986,p. 44.
  7. ^Eyes & Lichty 1986,p. 45.
  8. ^Application Specific Logic Products Data Book 1988.VLSI Technology Inc. 1988. pp. 257–279.Retrieved18 March2024.
  9. ^"W65C265S 16-bit Microcontroller".The Western Design Center, Inc.5 Jan 2021.Archivedfrom the original on 2 Apr 2024.Retrieved7 Apr2024.
  10. ^"W65C816 8/16-bit Microprocessor".The Western Design Center, Inc.5 Jan 2021.Archivedfrom the original on 15 Nov 2023.Retrieved7 Apr2024.
  11. ^"W65C265S 8/16-bit Microcontroller".The Western Design Center, Inc.5 Jan 2021.Archivedfrom the original on 7 Apr 2024.Retrieved7 Apr2024.
  12. ^"W55V92 TV-toy Controller Data Sheet"(PDF).Arrow Electronics.2 May 2006.Retrieved12 June2024.
  13. ^abEyes & Lichty 1986,p. 46.
  14. ^Eyes & Lichty 1986,p. 52.
  15. ^Eyes & Lichty 1986,p. 53.
  16. ^Eyes & Lichty 1986,p. 54.
  17. ^Eyes & Lichty 1986,p. 55.
  18. ^Eyes & Lichty 1986,p. 80.
  19. ^Eyes & Lichty 1986,p. 64.
  20. ^Eyes & Lichty 1986,p. 65.
  21. ^Eyes & Lichty 1986,p. 51.
  22. ^"16bits CPU – New Retro Computers".Foenix Retro Systems.
  23. ^"F256K".Foenix Retro Systems.

Bibliography

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Further reading

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See also:List of books about 65xx microprocessor families
  • 65C816 Datasheet;Western Design Center; 55 pages; 2018.
  • Eyes, David and Ron Lichty;Programming the 65816: Including the 6502, 65C02, and 65802;Brady Publishing; 636 pg; 2015
  • Fischer, Michael;65816/65802 assembly language programming;Osborne/McGraw-Hill; 686 pg; 1986
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