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Wafer-level packaging

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A wafer-level package attached to a printed-circuit board

Wafer-level packaging(WLP) is a process inintegrated circuit manufacturingwherepackagingcomponents are attached to anintegrated circuit(IC)beforethewafer– on which the IC is fabricated – isdiced.In WLP, the top and bottom layers of the packaging and the solder bumps are attached to the integrated circuits while they are still in the wafer. This process differs from a conventional process, in which the wafer is sliced into individual circuits (dice) before the packaging components are attached.

WLP is essentially a truechip-scale package(CSP) technology, since the resulting package is practically of the same size as the die. Wafer-level packaging allows integration of wafer fab, packaging, test, and burn-in at wafer level in order to streamline the manufacturing process undergone by a device from silicon start to customer shipment. As of 2009, there is no single industry-standard method of wafer-level packaging.

A major application area of WLPs is their use insmartphonesdue to the size constraints. For example, the AppleiPhone 5has at least eleven different WLPs, theSamsung Galaxy S3has six WLPs and theHTC One Xhas seven. Functions provided WLPs in smartphones include sensors, power management, and wireless.[1]The iPhone 7 was rumored to usefan-out wafer-level packagingtechnology in order to achieve a thinner and lighter model.[2][3][needs update]

Wafer-level chip scale packaging (WL-CSP) is the smallest package currently available on the market and is produced by OSAT (Outsourced Semiconductor Assembly and Test) companies, such asAdvanced Semiconductor Engineering (ASE).[4]A WL-CSP or WLCSP package is just a barediewith aredistribution layer(RDL,interposerorI/Opitch) to rearrange the pins or contacts on the die so that they can be big enough and have sufficient spacing so that they can be handled just like aball grid array(BGA) package.[5]The RDL is often made out of a polyamide or polybenzoxazole with copper plated on its surface.[6]

There are two kinds of wafer level packaging: fan-in and fan-out. Fan-in WLCSP packages have an interposer that is the same size as that of the die, where as fan-out WLCSP packages have an interposer that is larger than the die, similar to conventional BGA packages, the difference being that the interposer is built directly atop the die, instead of the die being attached to it and reflowed using the flip chip method. This is also true in fan-in WLSCP packages.[7][8]In both cases, the die with its interposer may be covered in encapsulating material such asepoxy.Fan.out packages are used in cases where fan-in packages are not able to provide enough connections at a specified cost.[9]

In February 2015, it was discovered that a WL-CSP chip in theRaspberry Pi 2had issues withxenon flashes(or any other bright flashes of longwave light), inducing thephotoelectric effectwithin the chip.[10]Thus, careful consideration concerning exposure to extremely bright light will need to be given with wafer-level packaging.

See also[edit]

References[edit]

  1. ^Korczynski, Ed (May 5, 2014)."Wafer-level packaging of ICs for mobile systems of the future".Semiconductor Manufacturing & Design Community.Archivedfrom the original on August 16, 2018.RetrievedSeptember 24,2018.
  2. ^By Aaron Mamiit, Tech Times. “Apple Wants a Slimmer iPhone 7 and Will Reportedly Use Fan-Out Packaging Technology.”April 1, 2016. Retrieved April 8, 2016.
  3. ^By Yoni Heisler, BGR. “Report details new tech Apple is using to make the iPhone 7 thinner and lighter.”March 31, 2016. Retrieved April 14, 2016.
  4. ^By Mark LaPedus, Semiconductor Engineering. “Fan-Out Packaging Gains Steam.”November 23, 2015. Retrieved May 23, 2016.
  5. ^"Wafer Level Chip Scale Package (WLCSP)"(PDF).nxp.Retrieved2023-11-19.
  6. ^https://semiengineering /improving-redistribution-layers-for-fan-out-packages-and-sips/
  7. ^"Stats ChipPAC - Wafer Level CSP (WLCSP) - a FIWLP Technology".statschippac.
  8. ^"WLCSP Overview, Market and Applications".November 11, 2018.
  9. ^https://semiengineering /fan-out-wars-begin/
  10. ^By Leon Spencer, ZDNet. “Raspberry Pi 2 power crashes when exposed to xenon flash.”February 9, 2015. Retrieved February 5, 2016.

Further reading[edit]

  • Shichun Qu; Yong Liu (2014).Wafer-Level Chip-Scale Packaging: Analog and Power Semiconductor Applications.Springer.ISBN978-1-4939-1556-9.
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