XNOR gate

XNOR gatetruth table
Input		Output
A	B	A XNOR B
0	0	1
0	1	0
1	0	0
1	1	1

TheXNOR gate(sometimesENOR,EXNOR,NXOR,XANDand pronounced asExclusive NOR) is a digitallogic gatewhose function is thelogical complementof the Exclusive OR (XOR) gate.^[1]It is equivalent to the logical connective ( $\leftrightarrow$ ) frommathematical logic,also known as the material biconditional. The two-input version implementslogical equality,behaving according to the truth table to the right, and hence the gate is sometimes called an "equivalence gate". A high output (1) results if both of the inputs to the gate are the same. If one but not both inputs are high (1), a low output (0) results.

Thealgebraic notationused to represent the XNOR operation is $S=A\odot B$ .The algebraic expressions $(A+{\overline {B}})\cdot ({\overline {A}}+B)$ and $A\cdot B+{\overline {A}}\cdot {\overline {B}}$ both represent the XNOR gate with inputsAandB.

Symbols

There aretwo symbols for XNOR gates:one with distinctive shape and one with rectangular shape and label. Both symbols for the XNOR gate are that of theXOR gatewith an added inversion bubble.

Distinctive symbol

Rectangular symbol

Hardware description

XNOR gates are represented in mostTTLandCMOS ICfamilies. The standard4000 seriesCMOS IC is the 4077, and the TTL IC is the 74266 (although anopen-collectorimplementation). Both include four independent, two-input, XNOR gates. The (now obsolete) 74S135 implemented four two-input XOR/XNOR gates or two three-input XNOR gates.

Both the TTL74LSimplementation, the 74LS266, as well as the CMOS gates (CD4077, 74HC4077 and 74HC266 and so on) are available from most semiconductor manufacturers such asTexas InstrumentsorNXP,etc.^[2]They are usually available in both through-holeDIPandSOICformats (SOIC-14, SOC-14 or TSSOP-14).

Datasheets are readily available in mostdatasheet databasesand suppliers.

Implementation

AND-OR-Invert logic

An XNOR gate can be implemented using a NAND gate and anOR-AND-Invertgate, as shown in the following picture.^[3] This is based on the identity

${\overline {a\veebar b}}\iff \left(a{\overline {\land }}b\right){\overline {\land }}\left(a\lor b\right)$

An alternative, which is useful when inverted inputs are also available (for example from aflip-flop), uses a 2-2AND-OR-Invertgate, shown on below on the right.

XNOR implemention using a NAND and an OAI gate
XNOR implementation using a 2-2-AOI gate with normal and inverted inputs

CMOS

CMOS implementations based on the OAI logic above can be realized with 10transistors,as shown below. The implementation which uses both normal and inverted inputs uses 8 transistors, or 12 if inverters have to be used.

An XNOR-gate in CMOS using a NAND and an OR-AND-Invert gate
An XNOR gate in CMOS using both normal and inverted inputs

Pinout

Both the 4077 and 74x266 devices (SN74LS266, 74HC266, 74266, etc.) have the same pinout diagram, as follows:

Pinout diagram of the 74HC266N, 74LS266 and CD4077 quad XNOR plasticdual in-line package14-pin package (PDIP-14)ICs.

Input A1
Input B1
Output Q1 (high if and only if A1 and B1 have the same logic level)
Output Q2
Input B2
Input A2
V_ss(GND) common power and signal ground pin
Input A3
Input B3
Output Q3
Output Q4
Input B4
Input A4
V_ddfor CMOS (V_ccfor TTL) positive power supply (see datasheets for acceptable voltage ranges)

Alternatives

If a specific type of gate is not available, a circuit that implements the same function can be constructed from other available gates. A circuit implementing an XNOR function can be trivially constructed from an XOR gate followed by a NOT gate. If we consider the expression $(A+{\overline {B}})\cdot ({\overline {A}}+B)$ ,we can construct an XNOR gate circuit directly using AND, OR and NOT gates. However, this approach requires five gates of three different kinds.

As alternative, if different gates are available we can applyBoolean algebrato transform $(A+{\overline {B}})\cdot ({\overline {A}}+B)\equiv (A\cdot B)+({\overline {A}}\cdot {\overline {B}})$ as stated above, and applyde Morgan's Lawto the last term to get $(A\cdot B)+{\overline {(A+B)}}$ which can be implemented using only three gates as shown on the right.

An XNOR gate circuit can be made from four NOR gates. In fact, both NAND and NOR gates are so-called "universal gates" and any logical function can be constructed from eitherNAND logicorNOR logicalone. If the four NOR gates are replaced by NAND gates, this results in an XOR gate, which can be converted to an XNOR gate by inverting the output or one of the inputs (e.g. with a fifth NAND gate).

Desired gate	NAND construction	NOR construction

An alternative arrangement is of five NAND gates in a topology that emphasizes the construction of the function from $(A\cdot B)+({\overline {A}}\cdot {\overline {B}})$ ,noting fromde Morgan's Lawthat a NAND gate is an inverted-input OR gate. Another alternative arrangement is of five NOR gates in a topology that emphasizes the construction of the function from $(A+{\overline {B}})\cdot ({\overline {A}}+B)$ ,noting fromde Morgan's Lawthat a NOR gate is an inverted-input AND gate.

Desired gate	NAND construction	NOR construction

For the NAND constructions, the lower arrangement offers the advantage of a shorter propagation delay (the time delay between an input changing and the output changing). For the NOR constructions, the upper arrangement requires fewer gates.

From the opposite perspective, constructing other gates using only XNOR gates is possible though XNOR is not a fullyuniversal logic gate.NOT and XOR gates can be constructed this way.

More than two inputs

Although other gates (OR, NOR, AND, NAND) are available from manufacturers with three or more inputs per gate, this is not strictly true with XOR and XNOR gates. However, extending the concept of thebinarylogical operation to three inputs, the SN74S135 with two shared "C" and four independent "A" and "B" inputs for its four outputs, was a device that followed the truth table:

Input			Output
A	B	C	Q
0	0	0	1
0	0	1	0
0	1	0	0
0	1	1	1
1	0	0	0
1	0	1	1
1	1	0	1
1	1	1	0

This is effectively Q = NOT ((A XOR B) XOR C). Another way to interpret this is that the output is true if an even number of inputs are true. It does not implement a logical "equivalence" function, unlike two-input XNOR gates.

References

^"Exclusive-NOR Gate Tutorial".Retrieved6 May2018.
^"XNOR Logic Gates".Retrieved6 May2018.
^Fischer, P."Aussagenlogik und Gatter"(PDF).University of Heidelberg.Retrieved2024-01-21.

External links

[:0-1] "Exclusive-NOR Gate Tutorial".Retrieved6 May2018.

[2] "XNOR Logic Gates".Retrieved6 May2018.

[3] Fischer, P."Aussagenlogik und Gatter"(PDF).University of Heidelberg.Retrieved2024-01-21.

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v t e Commonlogical connectives
Tautology/True $\top$
Alternative denial(NAND gate) $\uparrow$ Converse implication $\leftarrow$ Implication(IMPLY gate) $\rightarrow$ Disjunction(OR gate) $\lor$
Negation(NOT gate) $\neg$ Exclusive or(XOR gate) $\not \leftrightarrow$ Biconditional(XNOR gate) $\leftrightarrow$ Statement(Digital buffer)
Joint denial(NOR gate) $\downarrow$ Nonimplication(NIMPLY gate) $\nrightarrow$ Converse nonimplication $\nleftarrow$ Conjunction(AND gate) $\land$
Contradiction/False $\bot$
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