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HY29F080

8 Megabit (1M x 8), 5 Volt-only, Flash Memory

KEY FEATURES

n 5 Volt Read, Program, and Erase

– Minimizes system-level power

requirements

n Sector Group Protection

– Sectors may be locked in groups of two to

prevent program or erase operations

within that sector group

n High Performance

– Access times as fast as 70 ns

n Low Power Consumption

– 15 mA typical active read current

– 30 mA typical program/erase current

– 5 µA maximum CMOS standby current

n Compatible with JEDEC Standards

– Package, pinout and command-set

compatible with the single-supply Flash

device standard

n Temporary Sector Unprotect

– Allows changes in locked sectors

(requires high voltage on RESET# pin)

n Internal Erase Algorithm

– Automatically erases a sector, any

combination of sectors, or the entire chip

n Internal Programming Algorithm

– Automatically programs and verifies data

at a specified address

– Provides superior inadvertent write

protection

n Sector Erase Architecture

– Sixteen equal size sectors of 64K bytes

each

n Fast Program and Erase Times

– Byte programming time: 7 µs typical

– Sector erase time: 1.0 sec typical

– Chip erase time: 16 sec typical

n Data# Polling and Toggle Status Bits

– A command can erase any combination of

sectors

– Supports full chip erase

– Provide software confirmation of

completion of program or erase

operations

n Erase Suspend/Resume

– Temporarily suspends a sector erase

operation to allow data to be read from, or

programmed into, any sector not being

erased

n Ready/Busy# Pin

– Provides hardware confirmation of

completion of program and erase

operations

n Minimum 100,000 Program/Erase Cycles

n Space Efficient Packaging

– Available in industry-standard 40-pin

TSOP and 44-pin PSOP packages

GENERAL DESCRIPTION

LOGIC DIAGRAM

The HY29F080 is an 8 Megabit, 5 volt-only CMOS

Flash memory organized as 1,048,576 (1M) bytes

of eight-bits each. The device is offered in indus-

try-standard 44-pin PSOP and 40-pin TSOP pack-

ages.

20

8

A[19:0]

RESET#

CE#

DQ[7:0]

RY/BY#

The HY29F080 can be programmed and erased

in-system with a single 5-volt V_CCsupply. Inter-

nally generated and regulated voltages are pro-

vided for program and erase operations, so that

the device does not require a high voltage power

supply to perform those functions. The device can

also be programmed in standard EPROM pro-

grammers. Access times as fast as 70ns over the

full operating voltage range of 5.0 volts ± 10% are

offered for timing compatibility with the zero wait

state requirements of high speed microprocessors.

OE#

W E#

Revision 6.1, May 2001

HY29F080

To eliminate bus contention, the HY29F080 has

separate chip enable (CE#), write enable (WE#)

and output enable (OE#) controls.

the device has a Sector Group Protect function

which hardware write protects selected sector

groups. The sector group protect and unprotect

features can be enabled in a PROM programmer.

Temporary Sector Unprotect, which requires a high

voltage, allows in-system erasure and code

changes in previously protected sectors.

The device is compatible with the JEDEC single

power-supply Flash command set standard. Com-

mands are written to the command register using

standard microprocessor write timings, from where

they are routed to an internal state-machine that

controls the erase and programming circuits.

Device programming is performed a byte at a time

by executing the four-cycle Program Command.

This initiates an internal algorithm that automati-

cally times the program pulse widths and verifies

proper cell margin.

Erase Suspend enables the user to put erase on

hold for any period of time to read data from, or

program data to, any sector that is not selected

for erasure. True background erase can thus be

achieved. The device is fully erased when shipped

from the factory.

Addresses and data needed for the programming

and erase operations are internally latched during

write cycles, and the host system can detect

completion of a program or erase operation by

observing the RY/BY# pin, or by reading the DQ[7]

(Data# Polling) and DQ[6] (toggle) status bits.

Reading data from the device is similar to reading

from SRAM or EPROM devices. Hardware data

protection measures include a low V_CCdetector

that automatically inhibits write operations during

power transitions.

The HY29F080’s sector erase architecture allows

any number of array sectors to be erased and re-

programmed without affecting the data contents

of other sectors. Device erasure is initiated by

executing the Erase Command. This initiates an

internal algorithm that automatically preprograms

the array (if it is not already programmed) before

executing the erase operation. During erase

cycles, the device automatically times the erase

pulse widths and verifies proper cell margin.

To protect data in the device from accidental or

unauthorized attempts to program or erase the

device while it is in the system (e.g., by a virus),

The host can place the device into the standby

mode. Power consumption is greatly reduced in

this mode.

BLOCK DIAGRAM

DQ[7:0]

STATE

CONTROL

RY/BY#

ERASE VOLTAGE

GENERATOR AND

SECTOR SWITCHES

I/O BUFFERS

DATA LATCH

Y-GATING

DQ[7:0]

COMMAND

REGISTER

WE#

I/O CONTROL

CE#

ELECTRONIC

OE#

ID

PROGRAM

VOLTAGE

RESET#

GENERATOR

Y-DECODER

X-DECODER

V_SS

8 Mbit FLASH

MEMORY

ARRAY

V_{C C}

V_{C C}DETECTOR

TIMER

(16 x 512 Kbit

Sectors)

A[19:0]

Rev. 6.1/May 01

2

HY29F080

PIN CONFIGURATIONS

NC

RESET#

A11

1

2

3

4

5

6

7

44

43

42

41

40

39

38

V _CC

CE#

A12

A13

A14

A15

A16

A19

A18

A17

A16

A15

A14

A13

1

2

3

4

5

6

7

40

NC

39

38

37

36

35

34

NC

W E #

OE#

RY/BY#

DQ7

DQ6

A10

A9

A8

A7

A6

A5

8

9

37

36

A17

A18

A12

CE#

8

9

33

32

DQ5

DQ4

A4

NC

10

11

12

13

14

15

16

17

18

19

20

35

34

33

32

31

30

29

28

27

26

25

A19

NC

V _CC

NC

10

11

12

13

14

15

16

17

18

19

20

31

30

29

28

27

26

25

24

23

22

21

V _CC

V _SS

DQ3

DQ2

DQ1

DQ0

A0

Standard

TSOP40

NC

RESET#

A11

A10

A9

A3

NC

A2

NC

A1

W E #

OE#

RY/BY#

DQ7

DQ6

DQ5

A0

A8

DQ0

DQ1

DQ2

DQ3

A7

A6

A1

A5

A2

A4

A3

V _SS

21

22

24

23

DQ4

V _CC

NC

1

40

39

38

37

36

35

34

A19

A18

A17

A16

A15

A14

A13

2

3

4

5

6

7

W E #

OE#

RY/BY#

DQ7

DQ6

DQ5

DQ4

8

9

33

32

A12

CE#

V _CC

V _SS

10

11

12

13

14

15

31

30

29

28

27

26

V _CC

NC

Reverse

TSOP40

V _SS

RESET#

A11

DQ3

DQ2

DQ1

A10

A9

DQ0

A0

16

17

18

19

20

25

24

23

22

21

A8

A7

A6

A5

A4

A1

A2

A3

Rev. 6.1/May 01

3

HY29F080

CONVENTIONS

Unless otherwise noted, a positive logic (active

High) convention is assumed throughout this docu-

ment, whereby the presence at a pin of a higher,

more positive voltage (nominally 5VDC) causes

assertion of the signal. A ‘#’ symbol following the

signal name, e.g., RESET#, indicates that the sig-

nal is asserted in a Low state (nominally 0 volts).

Whenever a signal is separated into numbered

bits, e.g., DQ[7], DQ[6], ..., DQ[0], the family of

bits may also be shown collectively, e.g., as

DQ[7:0].

The designation 0xNNNN (N = 0, 1, 2, . . . , 9, A, .

. . , E, F) indicates a number expressed in hexa-

decimal notation. The designation 0bXXXX indi-

cates a number expressed in binary notation (X =

0, 1).

SIGNAL DESCRIPTIONS

Name

Type

Description

Address, active High. These twenty inputs select one of 1,048,576 (1M) bytes

within the array for read or write operations. A[19] is the MSB and A[0] is the

LSB.

A[19:0]

Inputs

Inputs/Outputs Data Bus, active High. These pins provide an 8-bit data path for read and write

DQ[7:0]

CE#

Tri-state

operations.

Chip Enable, active Low. This input must be asserted to read data from or

write data to the HY29F080. WhenHigh, the data bus is tri-stated and the device

is placed in the Standby mode.

Input

Output Enable, active Low. This input must be asserted for read operations

and negated for write operations. When High, data outputs from the device are

disabled and the data bus pins are placed in the high impedance state.

OE#

WE#

Input

Write Enable, active Low. Controls writing of commands or command

sequences in order to program data or erase sectors of the memory array. A

write operation takes place when WE# is asserted while CE# is Low and OE#

is High.

Hardware Reset, active Low. Provides a hardware method of resetting the

HY29F080 to the read array state. When the device is reset, it immediately

terminates any operationinprogress. The data bus is tri-stated and all read/write

commands are ignored while the input is asserted. While RESET# is asserted,

the device will be in the Standby mode.

RESET#

RY/BY#

Input

Ready/Busy Status. Indicates whether a write or erase command is in

progress or has been completed. RY/BY# is valid after the rising edge of the

final WE# pulse of a command sequence. It remains Low while the device is

actively programming data or erasing, and goes High when it is ready to read

array data.

Output

Open Drain

5-volt power supply.

V_CC

V_SS

--

Power and signal ground.

MEMORY ARRAY ORGANIZATION

erasure. See ‘Bus Operations’ and ‘Command

Definitions’ sections of this document for additional

information on these functions.

The 1 MByte Flash memory array is organized into

sixteen 64 KByte blocks called sectors (S0, S1, . .

. , S15). A sector is the smallest unit that can be

erased. Adjacent pairs of sectors (S0/S1, S2/S3,

. . . , S14/S15) are designated as a sector group.

A sector group is the smallest unit which can be

protected to prevent accidental or unauthorized

Table 1 defines the sector addresses, sector group

addresses and corresponding address ranges for

the HY29F080.

Rev. 6.1/May 01

4

HY29F080

Table 1. HY29F080 Memory Array Organization

Sector/Sector Group Address ¹

Sector

Group

Sector

Address Range A[19:0]

A[19]

0

A[18]

0

A[17]

0

A[16]

0

S0

S1

0x00000 - 0x0FFFF

0x10000 - 0x1FFFF

0x20000 - 0x2FFFF

0x30000 - 0x3FFFF

0x40000 - 0x4FFFF

0x50000 - 0x5FFFF

0x60000 - 0x6FFFF

0x70000 - 0x7FFFF

0x80000 - 0x8FFFF

0x90000 - 0x9FFFF

0xA0000 - 0xAFFFF

0xB0000 - 0xBFFFF

0xC0000 - 0xCFFFF

0xD0000 - 0xDFFFF

0xE0000 - 0xEFFFF

0xF0000 - 0xFFFFF

SG0

SG1

SG2

SG3

SG4

SG5

SG6

SG7

0

1

S2

0

1

0

S3

0

1

S4

0

1

0

S5

0

1

0

1

S6

0

1

0

S7

0

1

S8

1

0

S9

1

0

1

S10

S11

S12

S13

S14

S15

1

0

1

0

1

0

1

0

1

0

1

0

1

Notes:

1. A[19:16] are the sector address. A[19:17] are the sector group address.

BUS OPERATIONS

Device bus operations are initiated through the

internal command register, which consists of sets

of latches that store the commands, along with

the address and data information, if any, needed

to execute the specific command. The command

register itself does not occupy any addressable

memory location. The contents of the command

register serve as inputs to an internal state ma-

chine whose outputs control the operation of the

device. Table 2 lists the normal bus operations,

the inputs and control levels they require, and the

resulting outputs. Certain bus operations require

a high voltage on one or more device pins. Those

are described in Table 3.

Table 2. HY29F080 Normal Bus Operations ¹

Operation

CE#

OE#

L

WE#

H

RESET#

A[19:0]

DQ[7:0]

D_OUT

Read

Write

L

H

A_IN

X

L

H

L

H

D_IN

Output Disable

L

H

High-Z

CE# TTL Standby

H

X

H

V_CC± 0.3V

L

X

CE# CMOS Standby

Hardware Reset (TTL Standby)

Hardware Reset (CMOS Standby)

Notes:

V

_CC± 0.3V

X

V_SS± 0.5V

X

1. L = V_IL, H = V_IH, X = Don’t Care, D_OUT= Data Out, D_IN= Data In. See DC Characteristics for voltage levels.

Rev. 6.1/May 01

5

HY29F080

Table 3. HY29F080 Bus Operations Requiring High Voltage^{1, 2}

RESET-

Operation ³

CE#

L

OE# WE#

A[19:17] A[9]

A[6]

X

A[1]

X

A[0]

X

DQ[7:0]

#

Sector Group

Protect

V_ID

X

H

SGA ⁴

V_ID

X

Sector Group

Unprotect

V_ID

H

X

Temporary

Sector Group

Unprotect

X

V_ID

X

Manufacturer

Code

L

H

X

V_ID

L

Hynix = 0xAD

HY29F080 =

0xD5

Device Code

H

0x00 =

Unprotected

Sector Group

Protection

Verification

L

H

SGA ⁴

V_ID

L

H

L

0x01 =

Protected

Notes:

1. L = V_IL, H = V_IH, X = Don’t Care. See DC Characteristics for voltage levels.

2. Address bits not specified are Don’t Care.

3. See text for additional information.

4. SGA = sector group address. See Table 1.

Read Operation

instead of array data. After completing a program-

ming operation in the Erase Suspend mode, the

system may once again read array data with the

same exceptions noted above. After completing

an internal program or internal erase algorithm,

the HY29F080 automatically returns to the read

array data mode.

Data is read from the HY29F080 by using stan-

dard microprocessor read cycles while placing the

address of the byte to be read on the device’s

address inputs, A[19:0]. As shown in Table 2, the

host system must drive the CE# and OE# inputs

Low and drive WE# High for a valid read opera-

tion to take place. The device outputs the speci-

fied array data on DQ[7:0].

The host must issue a hardware reset or the soft-

ware reset command (see Command Definitions)

to return a sector to the read array data mode if

DQ[5] goes high during a program or erase cycle,

or to return the device to the read array data mode

while it is in the Electronic ID mode.

The HY29F080 is automatically set for reading

array data after device power-up and after a hard-

ware reset to ensure that no spurious alteration of

the memory content occurs during the power tran-

sition. No command is necessary in this mode to

obtain array data, and the device remains enabled

for read accesses until the command register con-

tents are altered.

Write Operation

Certain operations, including programming data

and erasing sectors of memory, require the host

to write a command or command sequence to the

HY29F080. Writes to the device are performed

by placing the byte address on the device’s ad-

dress inputs while the data to be written is input

on DQ[7:0]. The host system must drive the CE#

and WE# pins Low and drive OE# High for a valid

write operation to take place. All addresses are

This device features an Erase Suspend mode.

While in this mode, the host may read the array

data from any sector of memory that is not marked

for erasure. If the host attempts to read from an

address within an erase-suspended sector, or

while the device is performing an erase or byte

program operation, the device outputs status data

Rev. 6.1/May 01

6

HY29F080

latched on the falling edge of WE# or CE#, which-

ever happens later. All data is latched on the ris-

ing edge of WE# or CE#, whichever happens first.

the duration of the RESET# pulse. The device also

resets the internal state machine to reading array

data. If an operation was interrupted by the as-

sertion of RESET#, it should be reinitiated once

the device is ready to accept another command

sequence to ensure data integrity.

The ‘Device Commands’ section of this document

provides details on the specific device commands

implemented in the HY29F080.

Current is reduced for the duration of the RESET#

pulse as described in the Standby Operation sec-

tion above.

Output Disable Operation

When the OE# input is at V_IH, output data from the

device is disabled and the data bus pins are placed

in the high impedance state.

If RESET# is asserted during a program or erase

operation (RY/BY# pin is Low), the internal reset

operation is completed within a time of t_READY(during

Automatic Algorithms). The RY/BY# pin will go High

during the t_READYinterval, and the system can per-

form a read or write operation after waiting for a mini-

mum of t_READYor until t_RHafter the RESET# pin re-

turns High, whichever is longer. If RESET# is as-

serted when a program or erase operation is not

executing (RY/BY# pin is High), the reset operation

is completed within a time of t_RP. In this case, the

host can perform a read or write operation t_RHafter

the RESET# pin returns High.

Standby Operation

When the system is not reading from or writing to

the HY29F080, it can place the device in the

Standby mode. In this mode, current consump-

tion is greatly reduced, and the data bus outputs

are placed in the high impedance state, indepen-

dent of the OE# input. The Standby mode can

invoked using two methods.

The device enters the CE# CMOS Standby mode

if the CE# and RESET# pins are both held at V_CC

± 0.5V. Note that this is a more restricted voltage

range than V_IH. If both CE# and RESET# are held

High, but not within V_CC± 0.5V, the device will be

in the CE# TTL Standby mode, but the standby

current will be greater.

The RESET# pin may be tied to the system reset

signal. Thus, a system reset would also reset the

device, enabling the system to read the boot-up

firmware from the Flash memory.

Sector Group Protect/Unprotect Operations

The device enters the RESET# CMOS Standby

mode when the RESET# pin is held at V_SS± 0.5V.

If RESET# is held Low but not within V_SS± 0.5V,

the HY29F080 will be in the RESET# TTL Standby

mode, but the standby current will be greater. See

Hardware Reset Operation section for additional

information on the reset operation.

Hardware sector group protection can be invoked

to disable program and erase operations in any

single sector group or combination of sector

groups. This function is typically used to protect

data in the device from unauthorized or acciden-

tal attempts to program or erase the device while

it is in the system (e.g., by a virus) and is imple-

mented using programming equipment. Sector

group unprotection re-enables the program and

erase operations in previously protected sectors.

The device requires standard access time (t_CE) for

read access when the device is in either of the

standby modes, before it is ready to read data. If

the device is deselected during erasure or pro-

gramming, it continues to draw active current until

the operation is completed.

Table 1 identifies the eight sector groups and the

address ranges that each covers. The device is

shipped with all sector groups unprotected.

Hardware Reset Operation

The sector group protect/unprotect operations re-

quire a high voltage (V_ID) on address pin A9 and

the CE# and/or OE# control pins, as detailed in

Table 3. When implementing these operations,

note that V_CCmust be applied to the device before

applying V_ID, and that V_IDshould be removed be-

fore removing V_CCfrom the device.

The RESET# pin provides a hardware method of

resetting the device to reading array data. When

the RESET# pin is driven Low for the minimum

specified period, the device immediately termi-

nates any operation in progress, tri-states the data

bus pins, and ignores all read/write commands for

Rev. 6.1/May 01

7

HY29F080

The flow chart in Figure 1 illustrates the proce-

dure for protecting sector groups, and timing speci-

fications and waveforms are shown in the specifi-

cations section of this document. Verification of

protection is accomplished as described in the

Electronic ID Mode section and shown in the flow

chart.

the appropriate commands (see Device Com-

mands section). Once V_IDis removed from RE-

SET#, all the previously protected sectors are pro-

tected again. Figure 3 illustrates the algorithm.

Electronic ID Mode Operation

The Electronic ID mode provides manufacturer and

device identification and sector group protection

verification through identifier codes output on

DQ[7:0]. This mode is intended primarily for pro-

gramming equipment to automatically match a

device to be programmed with its corresponding

programming algorithm. The Electronic ID infor-

mation can also be obtained by the host through

a command sequence, as described in the De-

vice Commands section.

The procedure for sector group unprotection is il-

lustrated in the flow chart in Figure 2, and timing

specifications and waveforms are given at the end

of this document. Note that to unprotect any sec-

tor group, all unprotected sector groups must first

be protected prior to the first unprotect write cycle.

Sectors can also be temporarily unprotected as

described in the next section.

Temporary Sector Group Unprotect Operation

Operation in the Electronic ID mode requires V_ID

on address pin A[9], with additional requirements

for obtaining specific data items as listed in Table

2:

This feature allows temporary unprotection of pre-

viously protected sectors to allow changing the

data in-system. Temporary Sector Group Unpro-

tect mode is activated by setting the RESET# pin

to V_ID. While in this mode, formerly protected sec-

tors can be programmed or erased by invoking

n A read cycle at address 0xXXX00 retrieves the

manufacturer code (Hynix = 0xAD).

START

Wait t _WPP1

APPLY V

WE# = V

CC

IH

A9 = V _ID

A[19:17] = Group to Protect

OE# = CE# = A6 = A0 = V

A1 = V _IH

Set TRYCNT = 1

Increment TRYCNT

IL

Read Data

NO

Set A9 = OE# = V

ID

NO

Data = 0x01?

TRYCNT = 25?

YES

Set Address:

A[19:17] = Group to Protect

CE# = V

IL

YES

RESET# = V

IH

Remove V

from A9

ID

NO

Protect Another

Sector?

WE# = V

IL

SECTOR PROTECT

COMPLETE

DEVICE FAILURE

YES

Figure 1. Sector Group Protect Procedure

Rev. 6.1/May 01

8

HY29F080

START

NOTE: All sectors must be

previously protected.

Increment TRYCNT

Set Sector Group Address:

A[19:17] = Group NGRP

A0 = A6 = V

A1 = V _IH

APPLY V

IL

CC

Set: TRYCNT = 1

Read Data

NO

Set: NGRP = 0

YES

NO

Data = 0x00?

TRYCNT = 1000?

Set: A9 = CE# = OE# = V

ID

YES

Set: RESET# = V

IH

YES

WE# = V _IL

Wait t _WPP2

WE# = V _IH

NGRP = 7?

Remove V

from A9

ID

NO

NGRP = NGRP + 1

SECTOR UNPROTECT

COMPLETE

DEVICE FAILURE

Set:

A9 = V _ID

OE# = CE# = V

IL

Figure 2. Sector Group Unprotect Procedure

n A read cycle at address 0xXXX01 returns the

device code (HY29F080 = 0xD5).

START

n A read cycle containing a sector group address

(Table 1) in A[19:17] and the address 0x02 in

A[7:0] returns 0x01 if that sector is protected,

or 0x00 if it is unprotected.

RESET# = V_ID

(All protected sector groups

become unprotected)

Perform Program or Erase

Operations

RESET# = V_IH

(All previously protected

sector groups return to

protected state)

TEMPORARY SECTOR

UNPROTECT COMPLETE

Figure 3. Temporary Sector Group Unprotect

Rev. 6.1/May 01

9

HY29F080

DEVICE COMMANDS

Note: When in the Electronic ID bus operation mode,

the device returns to the Read mode when V_IDis re-

moved from the A[9] pin. The Read/Reset command is

not required in this case.

Device operations are initiated by writing desig-

nated address and data command sequences into

the device. A command sequence is composed

of one, two or three of the following sub-segments:

an unlock cycle, a command cycle and a data

cycle. Table 4 summarizes the composition of the

valid command sequences implemented in the

HY29F080, and these sequences are fully de-

scribed in Table 5 and in the sections that follow.

n If DQ[5] (Exceeded Time Limit) goes High dur-

ing a program or erase operation, writing the

reset command returns the sectors to the Read

mode (or to the Erase Suspend mode if the

device was in Erase Suspend).

Writing incorrect address and data values or writ-

ing them in the improper sequence resets the

HY29F080 to the Read mode.

The Read/Reset command may also be used to

abort certain command sequences:

n In a Sector Erase or Chip Erase command se-

quence, the Read/Reset command may be

written at any time before erasing actually be-

gins, including, for the Sector Erase command,

between the cycles that specify the sectors to

be erased (see Sector Erase command de-

scription). This aborts the command and re-

sets the device to the Read mode. Once era-

sure begins, however, the device ignores Read/

Reset commands until the operation is com-

plete.

Table 4. Composition of Command Sequences

Number of Bus Cycles

Command

Sequence

Unlock Command

Data

Read/Reset 1

Read/Reset 2

Byte Program

Chip Erase

0

2

4

0

2

1

Note 1

1

Sector Erase

Erase Suspend

Erase Resume

Electronic ID

1 (Note 2)

n In a Program command sequence, the Read/

Reset command may be written between the

sequence cycles before programming actually

begins. This aborts the command and resets

the device to the Read mode, or to the Erase

Suspend mode if the Program command se-

quence is written while the device is in the

Erase Suspend mode. Once programming

begins, however, the device ignores Read/Re-

set commands until the operation is complete.

0

Note 3

Notes:

1. Any number of Flash array read cycles are permitted.

2. Additional data cycles may follow. See text.

3. Any number of Electronic ID read cycles are permitted.

Read/Reset 1, 2 Commands

n The Read/Reset command may be written be-

tween the cycles in an Electronic ID command

sequence to abort that command. As described

above, once in the Electronic ID mode, the

Read/ Reset command must be written to re-

turn to the Read mode.

The HY29F080 automatically enters the Read

mode after device power-up, after the RESET#

input is asserted and upon the completion of cer-

tain commands. Read/Reset commands are not

required to retrieve data in these cases.

A Read/Reset command must be issued in order

to read array data in the following cases:

Byte Program Command

The host processor programs the device a byte at

a time by issuing the Program command sequence

shown in Table 5. The sequence begins by writ-

ing two unlock cycles, followed by the Program

setup command and, lastly, a data cycle specify-

ing the program address and data. This initiates

the Automatic Programming algorithm, which pro-

vides internally generated program pulses and

n If the device is in the Electronic ID mode, a

Read/ Reset command must be written to re-

turn to the Read mode. If the device was in the

Erase Suspend mode when the device entered

the Electronic ID mode, writing the Read/Re-

set command returns the device to the Erase

Suspend mode.

Rev. 6.1/May 01

10

HY29F080

Rev. 6.1/May 01

11

HY29F080

verifies the programmed cell margin. The host is

not required to provide further controls or timings

during this operation. When the Automatic Pro-

gramming algorithm is complete, the device re-

turns to the Read mode. Several methods are

provided to allow the host to determine the status

of the programming operation, as described in the

Write Operation Status section.

Chip Erase Command

The Chip Erase command sequence consists of

two unlock cycles, followed by the erase com-

mand, two additional unlock cycles and then the

chip erase data cycle. During chip erase, all sec-

tors of the device are erased except protected

sector groups. The command sequence starts the

Automatic Erase algorithm, which preprograms

and verifies the entire memory, except for pro-

tected sector groups, for an all zero data pattern

prior to electrical erase. The device then provides

the required number of internally generated erase

pulses and verifies cell erasure within the proper

cell margins. The host system is not required to

provide any controls or timings during these op-

erations.

Commands written to the device during execution

of the Automatic Programming algorithm are ig-

nored. Note that a hardware reset immediately

terminates the programming operation. To en-

sure data integrity, the aborted program command

sequence should be reinitiated once the reset

operation is complete.

Programming is allowed in any sequence. Only

erase operations can convert a stored “0” to a “1”.

Thus, a bit cannot be programmed from a “0” back

to a “1”. Attempting to do so will set DQ[5] to “1”,

and the Data# Polling algorithm will indicate that

the operation was not successful. A Read/Reset

command or a hardware reset is required to exit

this state, and a succeeding read will show that

the data is still “0”.

Commands written to the device during execution

of the Automatic Erase algorithm are ignored. Note

that a hardware reset immediately terminates the

erase operation. To ensure data integrity, the

aborted chip erase command sequence should be

reissued once the reset operation is complete.

When the Automatic Erase algorithm is finished,

the device returns to the Read mode. Several

methods are provided to allow the host to deter-

mine the status of the erase operation, as de-

scribed in the Write Operation Status section.

Figure 4 illustrates the procedure for the Program

operation.

Figure 5 illustrates the Chip Erase procedure.

START

Issue PROGRAM

Command Sequence:

Last cycle contains

program Address/Data

Issue CHIP ERASE

Command Sequence

Check Programming Status

DQ[5] Error Exit

(See Write Operation Status

Check Erase Status

DQ[5] Error Exit

Section)

(See Write Operation Status

Section)

Normal Exit

NO

GO TO

CHIP ERASE COMPLETE

Last Byte Done?

ERROR RECOVERY

YES

Figure 5. Chip Erase Procedure

Sector Erase Command

PROGRAMMING

COMPLETE

GO TO

ERROR RECOVERY

The Sector Erase command sequence consists

of two unlock cycles, followed by the erase com-

mand, two additional unlock cycles and then the

sector erase data cycle, which specifies which

Figure 4. Programming Procedure

Rev. 6.1/May 01

12

HY29F080

sector is to be erased. As described later in this

section, multiple sectors can be specified for era-

sure with a single command sequence. During

sector erase, all specified sectors are erased se-

quentially. The data in sectors not specified for

erasure, as well as the data in any sectors speci-

fied for erasure but located within protected sec-

tor groups, is not affected by the sector erase op-

eration.

least one selected sector is not protected, the

erase operation erases the unprotected sectors,

and ignores the command for the selected sec-

tors that are protected.

The system can monitor DQ[3] to determine if the

50 µs sector erase time-out has expired, as de-

scribed in the Write Operation Status section. If

the time between additional sector erase data

cycles can be insured to be less than the time-

out, the system need not monitor DQ[3].

The Sector Erase command sequence starts the

Automatic Erase algorithm, which preprograms

and verifies the specified unprotected sectors for

an all zero data pattern prior to electrical erase.

The device then provides the required number of

internally generated erase pulses and verifies cell

erasure within the proper cell margins. The host

system is not required to provide any controls or

timings during these operations.

Any command other than Sector Erase or Erase

Suspend during the time-out period resets the

device to reading array data. The system must

then rewrite the command sequence, including any

additional sector erase data cycles. Once the

sector erase operation itself has begun, only the

Erase Suspend command is valid. All other com-

mands are ignored.

After the sector erase data cycle (the sixth bus

cycle) of the command sequence is issued, a sec-

tor erase time-out of 50 µs (typical), measured from

the rising edge of the final WE# pulse in that bus

cycle, begins. During this time, an additional sec-

tor erase data cycle, specifying the sector address

of another sector to be erased, may be written

into an internal sector erase buffer. This buffer

may be loaded in any sequence, and the number

of sectors specified may be from one sector to all

sectors. The only restriction is that the time be-

tween these additional data cycles must be less

than 50 µs, otherwise erasure may begin before

the last data cycle is accepted. To ensure that all

data cycles are accepted, it is recommended that

host processor interrupts be disabled during the

time that the additional cycles are being issued

and then be re-enabled afterwards.

As for the Chip Erase command, note that a hard-

ware reset immediately terminates the erase op-

eration. To ensure data integrity, the aborted Sec-

tor Erase command sequence should be reissued

once the reset operation is complete.

When the Automatic Erase algorithm terminates,

the device returns to the Read mode. Several

methods are provided to allow the host to deter-

mine the status of the erase operation, as de-

scribed in the Write Operation Status section.

Figure 6 illustrates the Sector Erase procedure.

Erase Suspend/Erase Resume Commands

The Erase Suspend command allows the system

to interrupt a sector erase operation to read data

from, or program data in, any sector not being

erased. The command causes the erase opera-

tion to be suspended in all sectors selected for

erasure. This command is valid only during the

sector erase operation, including during the 50 µs

time-out period at the end of the initial command

sequence and any subsequent sector erase data

cycles, and is ignored if it is issued during chip

erase or programming operations.

Note: The device is capable of accepting three ways

of invoking Erase Commands for additional sectors

during the time-out window. The preferred method,

described above, is the sector erase data cycle after

the initial six bus cycle command sequence. How-

ever, the device also accepts the following methods

of specifying additional sectors during the sector

erase time-out:

n Repeat the entire six-cycle command sequence, speci-

fying the additional sector in the sixth cycle.

n Repeat the last three cycles of the six-cycle command

sequence, specifying the additional sector in the third

cycle.

The HY29F080 requires a maximum of 15 µs to

suspend the erase operation if the Erase Suspend

command is issued during active sector erasure.

However, if the command is written during the time-

out, the time-out is terminated and the erase op-

eration is suspended immediately. Any sub-

sequent attempts to specify additional sectors for

If all sectors scheduled for erasing are within pro-

tected sector groups, the device returns to read-

ing array data after approximately 100 µs. If at

Rev. 6.1/May 01

13

HY29F080

START

Check Erase Status

(See Write Operation Status

Section)

DQ[5] Error Exit

Normal Exit

Write First Five Cycles of

SECTOR ERASE

Command Sequence

GO TO

ERROR RECOVERY

ERASE COMPLETE

Setup First (or Next) Sector

Address for Erase Operation

Write Last Cycle (SA/0x30)

of SECTOR ERASE

Command Sequence

Sectors which require erasure

but which were not specified in

this erase cycle must be erased

later using a new command

sequence

NO

Sector Erase

Time-out (DQ[3])

Expired?

Erase An

Additional Sector?

YES

NO

Figure 6. Sector Erase Procedure

erasure by writing the sector erase data cycle (SA/

0x30) will be interpreted as the Erase Resume

command (XXX/0x30), which will cause the Auto-

matic Erase algorithm to begin its operation. Note

that any other command during the time-out will

reset the device to the Read mode.

the Resume command are ignored. Another Erase

Suspend command can be written after the de-

vice has resumed erasing.

The host may also write the Electronic ID com-

mand sequence when the device is in the Erase

Suspend mode. The device allows reading Elec-

tronic ID codes even if the addresses used for the

ID read cycles are within erasing sectors, since

the codes are not stored in the memory array.

When the device exits the Electronic ID mode, the

device reverts to the Erase Suspend mode, and

is ready for another valid operation. See Electronic

ID section for more information.

Once the erase operation has been suspended,

the system can read array data from or program

data to any sector not selected for erasure. Nor-

mal read and write timings and command defini-

tions apply. Reading at any address within erase-

suspended sectors produces status data on

DQ[7:0]. The host can use DQ[7], or DQ[6] and

DQ[2] together, to determine if a sector is actively

erasing or is erase-suspended. See “Write Op-

eration Status” for information on these status bits.

Electronic ID Command

The Electronic ID operation intended for use in

programming equipment has been described pre-

viously. The host processor can also be obtain

the same data by using the Electronic ID com-

mand sequence shown in Table 5. This method

does not require V_IDon any pin. The Electronic ID

command sequence may be invoked while the

device is in the Read mode or the Erase Suspend

mode, but is invalid while the device is actively

programming or erasing.

After an erase-suspended program operation is

complete, the host can initiate another program-

ming operation (or read operation) within non-sus-

pended sectors. The host can determine the sta-

tus of a program operation during the erase-sus-

pended state just as in the standard programming

operation.

The system must write the Erase Resume com-

mand to exit the Erase Suspend mode and con-

tinue the sector erase operation. Further writes of

Rev. 6.1/May 01

14

HY29F080

The Electronic ID command sequence is initiated

by writing two unlock cycles, followed by the Elec-

tronic ID command. The device then enters the

Electronic ID mode, and:

mand sequence. Thus, for example, the host may

determine the protection status for all sector

groups by doing successive reads at address 0x02

while changing the SGA in A[19:17] for each cycle.

n A read cycle at address 0xXXX00 retrieves the

The system must write the Reset command to exit

the Electronic ID mode and return to the Read

mode, or to the Erase Suspend mode if the de-

vice was in that mode when the command se-

quence was issued.

manufacturer code (Hynix = 0xAD).

n A read cycle at address 0xXXX01 returns the

device code (29F080 = 0xD5).

n A read cycle containing a sector group address

(SGA) in A[19:17] and the address 0x02 in

A[7:0] returns 0x01 if that sector is protected,

or 0x00 if it is unprotected.

The host system may read at any address any

number of times, without initiating another com-

WRITE OPERATION STATUS

The HY29F080 provides a number of facilities to

determine the status of a program or erase op-

eration. These are the RY/BY# (Ready/Busy#)

pin and certain bits of a status word which can be

read from the device during the programming and

erase operations. Table 6 summarizes the status

indications and further detail is provided in the

subsections which follow.

Table 6. Write and Erase Operation Status Summary

1

Mode

Operation

Programming in progress

Programming completed

Erase in progress

DQ[7]

DQ[7]#

Data

0

DQ[6]

Toggle

Data ⁴

Toggle

Data ⁴

DQ[5]

0/1 ²

DQ[3]

N/A

DQ[2]

N/A

RY/BY#

0

1

0

1

Data

0/1 ²

Data

1 ³

Data

Normal

Toggle

Data ⁴

Erase completed

1

Data

Read within erase suspended

sector

1

No toggle

Data

0

N/A

Toggle

Data

1

Read within non-erase

suspended sector

Erase

Data

Suspend

Programming in progress ⁵

Programming completed ⁵

DQ[7]#

Data

Toggle

Data ⁴

0/1 ²

N/A

0

1

Data

Notes:

1. A valid address is required when reading status information. See text for additional information.

2. DQ[5] status switches to a ‘1’ when a program or erase operation exceeds the maximum timing limit.

3. A ‘1’ during sector erase indicates that the 50 µs timeout has expired and active erasure is in progress. DQ[3] is not

applicable to the chip erase operation.

4. Equivalent to ‘No Toggle’ because data is obtained in this state.

5. Programming can be done only in a non-suspended sector (a sector not marked for erasure).

If the output is Low (busy), the device is actively

erasing or programming, including programming

while in the Erase Suspend mode. If the output is

High (ready), the device has completed the op-

eration and is ready to read array data in the nor-

mal or Erase Suspend modes, or it is in the standby

mode.

RY/BY# - Ready/Busy#

RY/BY# is an open-drain output pin that indicates

whether a programming or erase Automatic Algo-

rithm is in progress or has completed. A pull-up

resistor to V_CCis required for proper operation. RY/

BY# is valid after the rising edge of the final WE#

pulse in the corresponding command sequence.

Rev. 6.1/May 01

15

HY29F080

DQ[7] - Data# Polling

START

The Data# (“Data Bar”) Polling bit, DQ[7], indicates

to the host system whether an Automatic Algo-

rithm is in progress or completed, or whether the

device is in Erase Suspend mode. Data# Polling

is valid after the rising edge of the final WE# pulse

in the Program or Erase command sequence.

Read DQ[7:0]

at Valid Address (Note 1)

Test for DQ[7] = 1?

for Erase Operation

DQ[7] = Data?

NO

YES

The system must do a read at the program ad-

dress to obtain valid programming status informa-

tion on this bit. While a programming operation is

in progress, the device outputs the complement

of the value programmed to DQ[7]. When the pro-

gramming operation is complete, the device out-

puts the value programmed to DQ[7]. If a pro-

gram operation is attempted within a protected

sector, Data# Polling on DQ[7] is active for ap-

proximately 2 µs, then the device returns to read-

ing array data.

NO

DQ[5] = 1?

YES

Read DQ[7:0]

at Valid Address (Note 1)

Test for DQ[7] = 1?

for Erase Operation

The host must read at an address within any non-

protected sector scheduled for erasure to obtain

valid erase status information on DQ[7]. During

an erase operation, Data# Polling produces a “0”

on DQ[7]. When the erase operation is complete,

or if the device enters the Erase Suspend mode,

Data# Polling produces a “1” on DQ[7]. If all sec-

tors selected for erasing are protected, Data#

Polling on DQ[7] is active for approximately 100

µs, then the device returns to reading array data.

If at least one selected sector is not protected, the

erase operation erases the unprotected sectors,

and ignores the command for the selected sec-

tors that are protected.

DQ[7] = Data?

(Note 2)

YES

NO

PROGRAM/ERASE

EXCEEDED TIME ERROR

PROGRAM/ERASE

COMPLETE

Notes:

1. During programming, the program address.

During sector erase, an address within any non-protected sector

scheduled for erasure.

During chip erase, an address within any non-protected sector.

2. Recheck DQ[7] since it may change asynchronously at the same time

as DQ[5].

Figure 7. Data# Polling Test Algorithm

When the system detects that DQ[7] has changed

from the complement to true data (or “0” to “1” for

erase), it should do an additional read cycle to read

valid data from DQ[7:0]. This is because DQ[7]

may change asynchronously with respect to the

other data bits while Output Enable (OE#) is as-

serted low.

erase time-out. The system may use either OE#

or CE# to control the read cycles.

Successive read cycles at any address during an

Automatic Program algorithm operation (including

programming while in Erase Suspend mode)

cause DQ[6] to toggle. DQ[6] stops toggling when

the operation is complete. If a program address

falls within a protected sector, DQ[6] toggles for

approximately 2 µs after the program command

sequence is written, then returns to reading array

data.

Figure 7 illustrates the Data# Polling test algorithm.

DQ[6] - Toggle Bit I

Toggle Bit I on DQ[6] indicates whether an Auto-

matic Program or Erase algorithm is in progress

or complete, or whether the device has entered

the Erase Suspend mode. Toggle Bit I may be

read at any address, and is valid after the rising

edge of the final WE# pulse in the program or erase

command sequence, including during the sector

While the Automatic Erase algorithm is operating,

successive read cycles at any address cause

DQ[6] to toggle. DQ[6] stops toggling when the

erase operation is complete or when the device is

placed in the Erase Suspend mode. The host may

use DQ[2] to determine which sectors are erasing

Rev. 6.1/May 01

16

HY29F080

START

DQ[5] = 1?

YES

Read DQ[7:0]

at Valid Address (Note 1)

NO

Read DQ[7:0]

at Valid Address (Note 1)

Read DQ[7:0]

at Valid Address (Note 1)

YES

NO

DQ[6] Toggled?

(Note 2)

NO

DQ[6] Toggled?

DQ[2] Toggled?

YES

NO

(Note 4)

NO

(Note 3)

YES

PROGRAM/ERASE

COMPLETE

PROGRAM/ERASE

EXCEEDED TIME ERROR

SECTOR BEING READ

IS IN ERASE SUSPEND

SECTOR BEING READ

IS NOT IN ERASE SUSPEND

Notes

:

1. During programming, the program address.

During sector erase, an address within any sector scheduled for erasure.

2. Recheck DQ[6] since toggling may stop at the same time as DQ[5] changes from 0 to 1.

3. Use this path if testing for Program/Erase status.

4. Use this path to test whether sector is in Erase Suspend mode.

Figure 8. Toggle Bit I and II Test Algorithm

or erase-suspended (see below). After an Erase

command sequence is written, if all sectors se-

lected for erasing are protected, DQ[6] toggles for

approximately 100 µs, then returns to reading ar-

ray data. If at least one selected sector is not

protected, the Automatic Erase algorithm erases

the unprotected sectors, and ignores the selected

sectors that are protected.

Thus, both status bits are required for sector and

mode information.

Figure 8 illustrates the operation of Toggle Bits I

and II.

DQ[5] - Exceeded Timing Limits

DQ[5] is set to a ‘1’ when the program or erase

time has exceeded a specified internal pulse count

limit. This is a failure condition that indicates that

the program or erase cycle was not successfully

completed. DQ[5] status is valid only while DQ[7]

or DQ[6] indicate that an Automatic Algorithm is

in progress.

DQ[2] - Toggle Bit II

Toggle Bit II, DQ[2], when used with DQ[6], indi-

cates whether a particular sector is actively eras-

ing or whether that sector is erase-suspended.

Toggle Bit II is valid after the rising edge of the

final WE# pulse in the command sequence. The

device toggles DQ[2] with each OE# or CE# read

cycle.

The DQ[5] failure condition will also be signaled if

the host tries to program a ‘1’ to a location that is

previously programmed to ‘0’, since only an erase

operation can change a ‘0’ to a ‘1’.

DQ[2] toggles when the host reads at addresses

within sectors that have been selected for erasure,

but cannot distinguish whether the sector is ac-

tively erasing or is erase-suspended. DQ[6], by

comparison, indicates whether the device is ac-

tively erasing or is in Erase Suspend, but cannot

distinguish which sectors are selected for erasure.

For both of these conditions, the host must issue

a Read/Reset command to return the device to

the Read mode.

Rev. 6.1/May 01

17

HY29F080

DQ[7] (Data# Polling) or DQ[6] (Toggle Bit I) to

ensure that the device has accepted the command

sequence, and then read DQ[3]. If DQ[3] is a ‘1’,

the internally controlled erase cycle has begun and

all further sector erase data cycles or commands

(other than Erase Suspend) are ignored until the

erase operation is complete. If DQ[3] is a ‘0’, the

device will accept a sector erase data cycle to mark

an additional sector for erasure. To ensure that

the data cycles have been accepted, the system

software should check the status of DQ[3] prior to

and following each subsequent sector erase data

cycle. If DQ[3] is high on the second status check,

the last data cycle might not have been accepted.

DQ[3] - Sector Erase Timer

After writing a Sector Erase command sequence,

the host may read DQ[3] to determine whether or

not an erase operation has begun. When the

sector erase time-out expires and the sector erase

operation commences, DQ[3] switches from a ‘0’

to a ‘1’. Refer to the “Sector Erase Command”

section for additional information. Note that the

sector erase timer does not apply to the Chip Erase

command.

After the initial Sector Erase command sequence

is issued, the system should read the status on

HARDWARE DATA PROTECTION

The HY29F080 provides several methods of pro-

tection to prevent accidental erasure or program-

ming which might otherwise be caused by spuri-

ous system level signals during V_CCpower-up and

power-down transitions, or from system noise.

These methods are described in the sections that

follow.

Write Pulse “Glitch” Protection

Noise pulses of less than 5 ns (typical) on OE#,

CE# or WE# do not initiate a write cycle.

Logical Inhibit

Write cycles are inhibited by asserting any one of

the following conditions: OE# = V_IL, CE# = V_IH, or

WE# = V_IH. To initiate a write cycle, CE# and WE#

must be a logical zero while OE# is a logical one.

Command Sequences

Commands that may alter array data require a

sequence of cycles as described in Table 5. This

provides data protection against inadvertent writes.

Power-Up Write Inhibit

If WE# = CE# = V_ILand OE# = V_IHduring power

up, the device does not accept commands on the

rising edge of WE#. The internal state machine is

automatically reset to the Read mode on power-

up.

Low V_CCWrite Inhibit

To protect data during V_CCpower-up and power-

down, the device does not accept write cycles

when V_CCis less than V_LKO(typically 3.7 volts). The

command register and all internal program/erase

circuits are disabled, and the device resets to the

Read mode. Writes are ignored until V_CCis greater

than V_LKO. The system must provide the proper

signals to the control pins to prevent unintentional

Sector Group Protection

Additional data protection is provided by the

HY29F080’s sector group protect feature, de-

scribed previously, which can be used to protect

sensitive areas of the Flash array from accidental

or unauthorized attempts to alter the data.

writes when V_CCis greater than V_LKO

.

Rev. 6.1/May 01

18

HY29F080

ABSOLUTE MAXIMUM RATINGS⁴

Symbol

Parameter

Value

Unit

ºC

T_STG

T_BIAS

Storage Temperature

Ambient Temperature with Power Applied

-65 to +125

-55 to +125

ºC

Voltage on Pin with Respect to V_SS

VCC¹

:

-2.0 to +7.0

-2.0 to +13.5

-2.0 to +7.0

V

V_IN2

A[9], OE#, RESET# ²

All Other Pins ¹

I_OS

Output Short Circuit Current ³

200

mA

Notes:

1. Minimum DC voltage on input or I/O pins is –0.5 V. During voltage transitions, input or I/O pins may undershoot V_SSto

-2.0V for periods of up to 20 ns. See Figure 9. Maximum DC voltage on input or I/O pins is V_CC+ 0.5 V. During voltage

transitions, input or I/O pins may overshoot to V_CC+2.0 V for periods up to 20 ns. See Figure 10.

2. Minimum DC input voltage on pins A[9], OE#, and RESET# is -0.5 V. During voltage transitions, A[9], OE#, and RESET#

may undershoot V_SSto –2.0 V for periods of up to 20 ns. See Figure 9. Maximum DC input voltage on these pins is +12.5

V which may overshoot to 13.5 V for periods up to 20 ns.

3. No more than one output at a time may be shorted to V_SS. Duration of the short circuit should be less than one second.

4. Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a

stress rating only; functional operation of the device at these or any other conditions above those indicated in the

operational sections of this data sheet is not implied. Exposure of the device to absolute maximum rating conditions for

extended periods may affect device reliability.

1

RECOMMENDED OPERATING CONDITIONS

Symbol

T_A

Parameter

Ambient Operating Temperature

Operating Supply Voltage

Value

0 to +70

Unit

ºC

V_CC

+4.50 to +5.50

V

Notes:

1. Recommended Operating Conditions define those limits between which the functionality of the device is guaranteed.

20 ns

V_CC+ 2.0 V

0.8 V

- 0.5 V

V_CC+ 0.5 V

2.0 V

- 2.0 V

20 ns

Figure 9. Maximum Undershoot Waveform

Figure 10. Maximum Overshoot Waveform

Rev. 6.1/May 01

19

HY29F080

DC CHARACTERISTICS

TTL/NMOS Compatible

Parameter

Description

Test Setup

Min

Typ

Max

Unit

V_IN= V_SSto V_CC,

I_LI

Input Load Current

±1.0

µA

V_CC= V_CCMax

V_CC= V_CCMax,

A[9] = 12.5 V

I_LIT

A[9] Input Load Current

50

µA

V_OUT= V_SSto V_CC,

V_CC= V_CCMax

I_LO

I_CC1

I_CC2

I_CC3

Output Leakage Current

±1.0

V_CCActive Read Current ¹

V_CCActive Write Current ^{2, 3}

CE# = V_IL, OE# = V_IH

25

40

60

mA

V_CCCE# Controlled

TTL Standby Current

V_CC= V_CCMax,

CE# = RESET# = V_IH

0.4

1.0

mA

V_CCRESET# Controlled

TTL Standby Current

V_CC= V_CCMax,

RESET# = V_IL

I_CC4

V_IL

V_IH

Input Low Voltage

Input High Voltage

-0.5

2.0

0.8

V

V_CC+ 0.5

Voltage for Electronic ID and

Temporary Sector Unprotect

V_ID

V_OL

V_OH

V

_CC= 5.0V

11.5

12.5

0.45

V

V_CC= V_CCMin,

Output Low Voltage

I_OL= 12.0ma

_CC= V_CCMin,

I_OH= -2.5 mA

V

Output High Voltage

2.4

3.2

V

V_LKO

Low V_CCLockout Voltage ³

4.2

Notes:

1. Includes both the DC Operating Current and the frequency dependent component at 6 MHz. The read component of the

_CCcurrent is typically less than 1 ma/MHz with OE# at V_IL.

I

2. I_CCactive while Automatic Erase or Automatic Program algorithm is in progress.

3. Not 100% tested.

Rev. 6.1/May 01

20

HY29F080

DC CHARACTERISTICS

CMOS Compatible

Parameter

Description

Test Setup

Min

Typ

Max

Unit

V_IN= V_SSto V_CC,

V_CC= V_CCMax

I_LI

Input Load Current

±1.0

50

µA

V_CC= V_CCMax,

A[9] = 12.5 V

I_LIT

A[9] Input Load Current

µA

V_OUT= V_SSto V_CC,

V_CC= V_CCMax

I_LO

I_CC1

I_CC2

I_CC3

Output Leakage Current

±1.0

V_CCActive Read Current ¹

V_CCActive Write Current ^{2, 3}

CE# = V_IL, OE# = V_IH

25

30

40

mA

V_CCCE# Controlled

CMOS Standby Current

V_CC= V_CCMax, CE# =

RESET# = V_CC0.5V

1

5

µA

V_CCRESET# Controlled

CMOS Standby Current

V_CC= V_CCMax,

RESET# = V_SS0.5V

I_CC4

V_IL

V_IH

Input Low Voltage

Input High Voltage

-0.5

0.8

V

0.7 x V_CC

V_CC+ 0.3

Voltage for Electronic ID and

Temporary Sector Unprotect

V_ID

V_CC= 5.0V

11.5

12.5

0.45

V

V_CC= V_CCMin,

I_OL= 12.0ma

V_OL

Output Low Voltage

V_CC= V_CCMin,

I_OH= -2.5 mA

0.85 x

V_CC

V_OH

Output High Voltage

V_CC= V_CCMin,

I_OH= -100 µA

V_CC- 0.4

3.2

V

V_LKO

Low V_CCLockout Voltage ³

4.2

Notes:

1. Includes both the DC Operating Current and the frequency dependent component at 6 MHz. The read component of the

_CCcurrent is typically less than 1 ma/MHz with OE# at V_IL.

I

2. I_CCactive while Automatic Erase or Automatic Program algorithm is in progress.

3. Not 100% tested.

KEY TO SWITCHING WAVEFORMS

WAVEFORM

INPUTS

OUTPUTS

Steady

Changing from H to L

Changing from L to H

Don't Care, Any Change Permitted

Does Not Apply

Changing, State Unknown

Centerline is High Impedance State

(High Z)

Rev. 6.1/May 01

21

HY29F080

TEST CONDITIONS

+ 5V

Table 7. Test Specifications

- 70

- 90

- 12

Test

Condition

Unit

2.7

KOhm

Output Load

1 TTL Gate

100

DEVICE

UNDER

TEST

Output Load Capacitance (C_L)

Input Rise and Fall Times

Input Signal Low Level

Input Signal High Level

pF

ns

V

All diodes

are

1N3064

or

equivalent

20

0.45

6.2

KOhm

C _L

2.4

V

Low Timing Measurement

Signal Level

0.8

2.0

V

High Timing Measurement

Signal Level

Figure 11. Test Setup

2.4 V

2.0 V

Measurement

Levels

Input

Output

0.8 V

0.45 V

HY29F080-70, -90, -12 Versions

Figure 12. Input Waveforms and Measurement Levels

Rev. 6.1/May 01

22

HY29F080

AC CHARACTERISTICS

Read Operations

Parameter

Speed Option

- 70 - 90 - 12

Description

Test Setup

Unit

JEDEC Std

t_AVAV

t_RCRead Cycle Time (Note 1)

Min

70

90

120

ns

CE# = V_IL

OE# = V_IL

t_AVQV

t_ACCAddress to Output Delay

Max

70

90

120

t_ELQV

t_EHQZ

t_GLQV

t_GHQZ

t_CEChip Enable to Output Delay

OE# = V_IL

Max

Min

70

20

30

20

90

20

35

20

0

120

30

ns

t_DFChip Enable to Output High Z (Note 1)

t_OEOutput Enable to Output Delay

CE# = V_IL

50

t_DFOutput Enable to Output High Z (Note 1)

30

Read

Output Enable

Hold Time (Note 1)

t_OEH

Toggle and

Data# Polling

Min

10

0

ns

Output Hold Time from Addresses, CE#

or OE#, Whichever Occurs First (Note 1)

t_AXQX

t_OH

Notes:

1. Not 100% tested.

2. See Figure 11 and Table 7 for test conditions.

t_RC

Addresses

CE#

Addresses Stable

t_ACC

t_OE

OE#

t_OEH

t_DF

WE#

Outputs

RESET#

t_CE

t_OH

Output Valid

RY/BY#

0 V

Figure 13. Read Operation Timings

Rev. 6.1/May 01

23

HY29F080

AC CHARACTERISTICS

Hardware Reset (RESET#)

Parameter

Speed Option

Description

Test Setup

Unit

JEDEC Std

- 70 - 90 - 12

RESET# Pin Low (During Automatic

t_READYAlgorithms) to Read or Write (see Note

1)

Max

20

µs

RESET# Pin Low (NOT During

t_READYAutomatic Algorithms) to Read or Write

(see Note 1)

500

ns

t_RPRESET# Pulse Width

Min

500

50

ns

RESET# High Time Before Read (see

t_RH

Note 1)

Notes:

1. Not 100% tested.

2. See Figure 11 and Table 7 for test conditions.

RY/BY#

0 V

CE#, OE#

RESET#

t_RH

t_RP

t_READY

Reset Timings NOT During Automatic Algorithms

RY/BY#

CE#, OE#

RESET#

t_READY

t_RP

t_RH

Reset Timings During Automatic Algorithms

Figure 14. RESET# Timings

Rev. 6.1/May 01

24

HY29F080

AC CHARACTERISTICS

Program and Erase Operations

Parameter

Speed Option

- 70 - 90 - 12

Description

Unit

JEDEC Std

t_AVAV

t_AVWL

t_WLAX

t_DVWH

t_WHDX

t_GHWL

t_ELWL

t_WHEH

t_WLWH

t_WHWL

t_WCWrite Cycle Time (Note 1)

Min

Typ

70

90

0

120

ns

t_ASAddress Setup Time

t_AHAddress Hold Time

t_DSData Setup Time

45

30

45

0

50

ns

t_DHData Hold Time

ns

t_GHWLRead Recovery Time Before Write

t_CSCE# Setup Time

0

ns

0

ns

t_CHCE# Hold Time

0

ns

t_WPWrite Pulse Width

t_WPHWrite Pulse Width High

35

45

20

7

50

ns

µs

t_WHWH1t_WHWH1Byte Programming Operation (Notes 1, 2, 3)

Chip Programming Operation (Notes 1, 2, 3, 5)

t_WHWH2t_WHWH2Sector Erase Operation (Notes 1, 2, 4)

t_WHWH3t_WHWH3Chip Erase Operation (Notes 1, 2, 4)

Erase and Program Cycle Endurance

Max

Typ

300

7.2

21.6

1

µs

sec

cycles

µs

Max

Typ

Max

Typ

8

16

128

Max

Typ

1,000,000

Min

100,000

t_VCSV_CCSetup Time

50

0

t_RBRecovery Time from RY/BY#

t_BUSYWE# to RY/BY# Delay

ns

40

50

ns

Notes:

1. Not 100% tested.

2. Typical program and erase times assume the following conditions: 25 °C, V_CC= 5.0 volts, 100,000 cycles. In addition,

programming typicals assume a checkerboard pattern. Maximum program and erase times are under worst case condi-

tions of 90 °C, V_CC= 4.5 volts, 100,000 cycles.

3. Excludes system-level overhead, which is the time required to execute the four-bus-cycle sequence for the program

command. See Table 5 for further information on command sequences.

4. Excludes 0x00 programming prior to erasure. In the preprogramming step of the Automatic Erase algorithm, all bytes

are programmed to 0x00 before erasure.

5. The typical chip programming time is considerably less than the maximum chip programming time listed since most

bytes program faster than the maximum programming times specified. The device sets DQ[5] = 1 only If the maximum

byte program time specified is exceeded. See Write Operation Status section for additional information.

Rev. 6.1/May 01

25

HY29F080

AC CHARACTERISTICS

Program Command Sequence (last two cycles)

Read Status Data (last two cycles)

t_{W C}

t_AS

t_AH

Addresses

CE#

0x555

PA

t_{G H W L}

OE#

t_CH

t_{W P}

WE#

t_CS

t_{W P H}

t_{W H W H 1}

Data

0xA0

PD

t_BUSY

Status

D_OUT

t_RB

t_DS

t_DH

RY/BY#

V_CC

t_VCS

Notes:

1. PA = Program Address, PD = Program Data, D_OUTis the true data at the program address.

2. V_CCshown only to illustrate t_VCSmeasurement references. It cannot occur as shown during a valid command sequence.

Figure 15. Program Operation Timings

Rev. 6.1/May 01

26

HY29F080

AC CHARACTERISTICS

Erase Command Sequence (last two cycles)

Read Status Data (last two cycles)

t_{W C}

t_AS

t_AH

Addresses

CE#

0x2AA

SA

VA

0x555 for chip erase

t_{G H W L}

OE#

t_CH

t_{W P}

WE#

t_{W H W H 2}or t_{W H W H 3}

Status

t_CS

t_{W P H}

0x10 for

chip erase

Data

0x55

0x30

t_BUSY

D_OUT

t_RB

t_DS

t_DH

RY/BY#

V_CC

t_VCS

Notes:

1. SA =Sector Address (for sector erase), VA = Valid Address for reading status data (see Write Operation Status section),

D_OUTis the true data at the read address.(0xFF after an erase operation).

2. V_CCshown only to illustrate t_VCSmeasurement references. It cannot occur as shown during a valid command sequence.

Figure 16. Sector/Chip Erase Operation Timings

Rev. 6.1/May 01

27

HY29F080

AC CHARACTERISTICS

t_RC

VA

Addresses

VA

t_ACC

t_CH

t_CE

CE#

t_OE

OE#

WE#

t_DF

t_OEH

t_OH

Complement

Status Data

Complement

True

Valid Data

DQ[7]

DQ[6:0]

RY/BY#

Status Data

True

t_BUSY

Notes:

1. VA = Valid Address for reading Data# Polling status data (see Write Operation Status section).

2. Illustration shows first status cycle after command sequence, last status read cycle and array data read cycle.

Figure 17. Data# Polling Timings (During Automatic Algorithms)

t_RC

Addresses

CE#

VA

t_ACC

t_CH

t_CE

t_OE

OE#

t_DF

t_OEH

WE#

t_OH

Valid Status

(first read)

Valid Status

(second read)

Valid Status

Valid Data

DQ[6], [2]

(stops toggling)

t_BUSY

RY/BY#

Notes:

1. VA = Valid Address for reading Toggle Bits (DQ2, DQ6) status data (see Write Operation Status section).

2. Illustration shows first two status read cycles after command sequence, last status read cycle and array data read cycle.

Figure 18. Toggle Polling Timings (During Automatic Algorithms)

Rev. 6.1/May 01

28

HY29F080

AC CHARACTERISTICS

Enter

Automatic

Erase

Enter Erase

Suspend

Program

Erase

Suspend

Erase

Resume

WE#

Erase

Suspend

Read

Suspend

Program

Suspend

Read

Complete

DQ[6]

DQ[2]

Notes:

1. The system may use CE# or OE# to toggle DQ[2] and DQ[6]. DQ[2] toggles only when read at an address within an

erase-suspended sector.

Figure 19. DQ[2] and DQ[6] Operation

Sector Group Protect and Unprotect, Temporary Sector Group Unprotect

Parameter

Speed Option

- 70 - 90 - 12

50

Description

Unit

JEDEC Std

t_STVoltage Setup Time

Min

µs

RESET# Setup Time for

Temporary Sector Group Unprotect

t_RSP

4

t_CEChip Enable to Output Delay

t_OEOutput Enable to Output Delay

Max

70

30

90

35

120

50

ns

Voltage Transition Time for

t_VIDR

Min

500

4

ns

µs

Temporary Sector Group Unprotect (Note 1)

Voltage Transition Time for

t_VLHT

Sector Group Protect and Unprotect (Note 1)

t_WPP1Write Pulse Width for Sector Group Protect

t_WPP2Write Pulse Width for Sector Group Unprotect

t_OESPOE# Setup Time to WE# Active (Note 1)

t_CSPCE# Setup Time to WE# Active (Note 1)

Min

100

4

µs

ms

µs

4

Notes:

1. Not 100% tested.

Rev. 6.1/May 01

29

HY29F080

AC CHARACTERISTICS

Group Protect Cycle

Protect Verify Cycle

A[19:17]

A[0]

SGA _X

SGA _Y

A[1]

A[6]

V_ID

A[9]

t_VLHT

V_ID

OE#

t_OESP

t_VLHT

t_WPP1

WE#

CE#

t_OE

Data

0x01

RESET#

t_ST

V_CC

t_ST

Figure 20. Sector Group Protect Timings

Rev. 6.1/May 01

30

HY29F080

AC CHARACTERISTICS

Group Unprotect Cycle

Unprotect Verify Cycle

A[19:17]

A[0]

SGA ₀

SGA ₁

A[1]

A[6]

V_ID

A[9]

t_VLHT

V_ID

OE#

t_OE

t_OESP

V_ID

CE#

t_CSP

t_WPP2

t_CE

WE#

Data

0x00

RESET#

V_CC

t_ST

Figure 21. Sector Group Unprotect Timings

Rev. 6.1/May 01

31

HY29F080

AC CHARACTERISTICS

V_ID

RESET#

0 or 5V

t_VIDR

CE#

WE#

t_RSP

RY/BY#

Figure 22. Temporary Sector Group Unprotect Timings

Rev. 6.1/May 01

32

HY29F080

AC CHARACTERISTICS

Alternate CE# Controlled Erase/Program Operations

Parameter

Description

JEDEC Std

Speed Option

- 70 - 90 - 12

Unit

t_AVAV

t_AVWL

t_WLAX

t_DVWH

t_WHDX

t_GHEL

t_WLEL

t_EHWH

t_ELEH

t_EHEL

t_WCWrite Cycle Time (Note 1)

t_ASAddress Setup Time

t_AHAddress Hold Time

t_DSData Setup Time

Min

Typ

70

90

0

120

ns

45

30

45

0

50

ns

t_DHData Hold Time

ns

t_GHELRead Recovery Time Before Write

t_WSWE# Setup Time

0

ns

0

ns

t_WHWE# Hold Time

0

ns

t_CPCE# Pulse Width

35

45

20

7

50

ns

t_CPHCE# Pulse Width High

ns

µs

t_WHWH1t_WHWH1Byte Programming Operation (Notes 1, 2, 3)

Chip Programming Operation (Notes 1, 2, 3, 5)

t_WHWH2t_WHWH2Sector Erase Operation (Notes 1, 2, 4)

t_WHWH3t_WHWH3Chip Erase Operation (Notes 1, 2, 4)

Erase and Program Cycle Endurance

Max

Typ

300

7.2

21.6

1

µs

sec

cycles

Max

Typ

Max

Typ

8

16

128

Max

Typ

1,000,000

100,000

Min

Notes:

1. Not 100% tested.

2. Typical program and erase times assume the following conditions: 25 °C, V_CC= 5.0 volts, 100,000 cycles. In addition,

programming typicals assume a checkerboard pattern. Maximum program and erase times are under worst case condi-

tions of 90 °C, V_CC= 4.5 volts, 100,000 cycles.

3. Excludes system-level overhead, which is the time required to execute the four-bus-cycle sequence for the program

command. See Table 5 for further information on command sequences.

4. Excludes 0x00 programming prior to erasure. In the preprogramming step of the Automatic Erase algorithm, all bytes

are programmed to 0x00 before erasure.

5. The typical chip programming time is considerably less than the maximum chip programming time listed since most

bytes program faster than the maximum programming times specified. The device sets DQ[5] = 1 only If the maximum

byte program time specified is exceeded. See Write Operation Status section for additional information.

Rev. 6.1/May 01

33

HY29F080

AC CHARACTERISTICS

PA for Program

SA for Sector Erase

0x555 for Chip Erase

0x555 for Program

0x2AA for Erase

Addresses

VA

t_{W C}

t_AS

t_AH

WE#

OE#

CE#

t_GHEL

t_{W H}

t_CP

t_CPH

t_{W H W H 1}or t_{W H W H 2}or t_{W H W H 3}

t_{W S}

t_DS

t_DH

t_BUSY

Data

Status

D _OUT

0xA0 for Program

0x55 for Erase

PD for Program

0x30 for Sector Erase

0x10 for Chip Erase

RY/BY#

t_RH

RESET#

Notes:

1. PA = program address, PD = program data, VA = Valid Address for reading program or erase status (see Write

Operation Status section), D_OUT= array data read at VA.

2. Illustration shows the last two cycles of the program or erase command sequence and the last status read cycle.

3. Word mode addressing shown.

4. RESET# shown only to illustrate t_RHmeasurement references. It cannot occur as shown during a valid

command sequence.

Figure 23. Alternate CE# Controlled Write Operation Timings

Rev. 6.1/May 01

34

HY29F080

Latchup Characteristics

Description

Minimum

- 1.0

Maximum

V_CC+ 1.0

100

Unit

V

Input voltage with respect to V_SSon all I/O pins

V_CCCurrent

- 100

mA

Notes:

1. Includes all pins except V_CC. Test conditions: V_CC= 5.0V, one pin at a time.

TSOP Pin Capacitance

Symbol

C_IN

Parameter

Input Capacitance

Test Setup

V_IN= 0

Typ

Max

7.5

12

Unit

pF

6

8.5

8

C_OUT

C_IN2

Output Capacitance

V_OUT= 0

V_IN= 0

pF

Control Pin Capacitance

9

pF

Notes:

1. Sampled, not 100% tested.

2. Test conditions: T_A= 25 ºC, f = 1.0 MHz.

PSOP Pin Capacitance

Symbol

C_IN

Parameter

Input Capacitance

Test Setup

V_IN= 0

Typ

6

Max

7.5

12

Unit

pF

C_OUT

C_IN2

Output Capacitance

V_OUT= 0

V_IN= 0

8.5

7.5

pF

Control Pin Capacitance

10

pF

Notes:

1. Sampled, not 100% tested.

2. Test conditions: T_A= 25 ºC, f = 1.0 MHz.

Data Retention

Parameter

Test Conditions

Minimum

Unit

Years

150 ºC

125 ºC

10

20

Minimum Pattern Data Retention Time

Rev. 6.1/May 01

35

HY29F080

PACKAGE DRAWINGS

Physical Dimensions

TSOP40 - 40-pin Thin Small Outline Package (measurements in millimeters)

0.95

1.05

Pin 1 ID

1

40

9.90

0.50 BSC

10.10

20

21

18.30

18.50

0.05

0.15

19.90

20.10

0.08

0.20

1.20

MAX

0.10

0.20

0^o

5^o

0.25 BSC

0.50

0.68

PSOP44 - 44-pin Plastic Small Outline Package (measurements in millimeters)

23

44

15.70

16.30

13.10

13.50

0.10

0.21

0^O

8^O

0.60

1.00

1

22

1.27 NOM.

28.00

28.40

2.17

2.45

2.80

MAX.

SEATING PLANE

0.10

0.35

0.50

Rev. 6.1/May 01

36

HY29F080

ORDERING INFORMATION

Hynix products are available in several speeds, packages and operating temperature ranges. The

ordering part number is formed by combining a number of fields, as indicated below. Refer to the ‘Valid

Combinations’ table, which lists the configurations that are planned to be supported in volume. Please

contact your local Hynix representative or distributor to confirm current availability of specific configura-

tions and to determine if additional configurations have been released.

HY29F080

X

-

X

SPECIAL INSTRUCTIONS

TEMPERATURE RANGE

Blank = Commercial ( 0 to +70 °C)

SPEED OPTION

70 = 70 ns

90 = 90 ns

12 = 120 ns

PACKAGE TYPE

G = 44-Pin Plastic Small Outline Package (PSOP)

T = 40-Pin Thin Small Outline Package (TSOP)

R = 40-Pin Thin Small Outline Package (TSOP) with

Reverse Pinout

DEVICE NUMBER

HY29F080 = 8 Megabit (1M x 8) CMOS 5-Volt Only Sector Erase

Flash Memory

VALID COMBINATIONS

Package and Speed

PSOP

TSOP

90 ns 120 ns 70 ns

T-90 T-12 R-70

Reverse TSOP

90 ns 120 ns

R-90 R-12

Temperature

70 ns

90 ns 120 ns 70 ns

Commercial

G-70

G-90

G-12

T-70

Note:

1. The complete part number is formed by appending the suffix shown in the table to the Device Number. For example, the

part number for a 90 ns, Commercial temperature range device in the TSOP package is HY29F080T-90.

Rev. 6.1/May 01

37

HY29F080

Important Notice

No part of this document may be copied or reproduced in any

form or by any means without the prior written consent of Hynix

Semiconductor Inc. or Hynix Semiconductor America (collec-

tively “Hynix”).

tions of Sale only. Hynix makes no warranty, express, statu-

tory, implied or by description, regarding the information set

forth herein or regarding the freedom of the described devices

from intellectual property infringement. Hynix makes no war-

ranty of merchantability or fitness for any purpose.

The information in this document is subject to change without

notice. Hynix shall not be responsible for any errors that may

appear in this document and makes no commitment to update

or keep current the information contained in this document.

Hynix advises its customers to obtain the latest version of the

device specification to verify, before placing orders, that the

information being relied upon by the customer is current.

Hynix’s products are not authorized for use as critical compo-

nents in life support devices or systems unless a specific writ-

ten agreement pertaining to such intended use is executed

between the customer and Hynix prior to use. Life support

devices or systems are those which are intended for surgical

implantation into the body, or which sustain life whose failure to

perform, when properly used in accordance with instructions

for use provided in the labeling, can be reasonably expected to

result in significant injury to the user.

Devices sold by Hynix are covered by warranty and patent in-

demnification provisions appearing in Hynix Terms and Condi-

Revision Record

Rev. Date

Details

Change to Hynix format.

Removed 55 ns speed option and Industrial and Extended temperature options.

6.1

5/01

Memory Sales and Marketing Division

Hynix Semiconductor Inc.

10 Fl., Hynix Youngdong Building

89, Daechi-dong

Flash Memory Business Unit

Hynix Semiconductor America Inc.

3101 North First Street

San Jose, CA 95134

USA

Kangnam-gu

Seoul, Korea

Telephone: (408) 232-8800

Fax: (408) 232-8805

Telephone: +82-2-580-5000

Fax: +82-2-3459-3990

http://www.us.hynix.com

http://www.hynix.com

Rev. 6.1/May 01

38

型号:	HY29F080T-12
是否Rohs认证：	不符合
生命周期：	Obsolete
零件包装代码：	TSOP
包装说明：	TSOP-40
针数：	40
Reach Compliance Code：	compliant
ECCN代码：	EAR99
HTS代码：	8542.32.00.51
风险等级：	5.52
最长访问时间：	120 ns
其他特性：	MINIMUM 100000 PROGRAM/ERASE CYCLES
命令用户界面：	YES
数据轮询：	YES
JESD-30 代码：	R-PDSO-G40
JESD-609代码：	e0
长度：	18.4 mm
内存密度：	8388608 bit
内存集成电路类型：	FLASH
内存宽度：	8
功能数量：	1
部门数/规模：	16
端子数量：	40
字数：	1048576 words
字数代码：	1000000
工作模式：	ASYNCHRONOUS
最高工作温度：	70 °C
最低工作温度：
组织：	1MX8
封装主体材料：	PLASTIC/EPOXY
封装代码：	TSOP1
封装等效代码：	TSOP40(UNSPEC)
封装形状：	RECTANGULAR
封装形式：	SMALL OUTLINE, THIN PROFILE
并行/串行：	PARALLEL
峰值回流温度（摄氏度）：	NOT SPECIFIED
电源：	5 V
编程电压：	5 V
认证状态：	Not Qualified
就绪/忙碌：	YES
座面最大高度：	1.2 mm
部门规模：	64K
最大待机电流：	0.000005 A
子类别：	Flash Memories
最大压摆率：	0.06 mA
最大供电电压 (Vsup)：	5.5 V
最小供电电压 (Vsup)：	4.5 V
标称供电电压 (Vsup)：	5 V
表面贴装：	YES
技术：	CMOS
温度等级：	COMMERCIAL
端子面层：	Tin/Lead (Sn/Pb)
端子形式：	GULL WING
端子节距：	0.5 mm
端子位置：	DUAL
处于峰值回流温度下的最长时间：	NOT SPECIFIED
切换位：	YES
类型：	NOR TYPE
宽度：	10 mm
Base Number Matches：	1

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