HY51V65164ATC-60全新原装原理图各脚功能电路原理芯片引脚定义-中国IC网-芯三七

HY51V64164A,HY51V65164A

4Mx16, Extended Data Out mode

2nd Generation

DESCRIPTION

This family is a 64M bit dynamic RAM organized 4,194,304 x 16-bit configuration with Extended Data Out mode CMOS

DRAMs. Extended data out mode is a kind of page mode which is useful for the read operation. The circuit and process

design allow this device to achieve high performance and low power dissipation. Optional features are access time(50 or

60ns) and refresh cycle(8K ref. or 4K ref.) and power consumption (Normal or Low power with self refresh). Hyundai’s

advanced circuit design and process technology allow this device to achieve high bandwidth, low power consumption and

high reliability.

FEATURES

Ÿ Extended data out operation

Ÿ JEDEC standard pinout

Ÿ Read-modify-write capability

50-pin plastic TSOP-II (400mil)

Ÿ Multi-bit parallel test capability

Ÿ Single power supply of 3.3 ± 0.3V

Ÿ LVTTL(3.3V) compatible inputs and outputs

Ÿ Early write or output enable controlled write

Ÿ /CAS-before-/RAS, /RAS-only, Hidden and

Self refresh capability

Ÿ Max. Active power dissipation

Ÿ Fast access time and cycle time

Speed

50

8K refresh

4K refresh

504mW

Speed

50

tRAC

50ns

60ns

tCAC

13ns

15ns

tHPC

20ns

25ns

396mW

324mW

60

432mW

60

Ÿ Refresh cycles

Part number

HY51V64164A¹⁾

HY51V65164A²⁾

Refresh

Normal

L-part

8K

4K

64ms

128ms

1) Normal read / write, /RAS only refresh : 8K cycles / 64ms

/CAS-before-/RAS, Hidden refresh : 4K cycles / 64ms

2) Normal read / write, /RAS only refresh : 4K cycles / 64ms

/CAS-before-/RAS, Hidden refresh

: 4K cycles / 64ms

ORDERING INFORMATION

Part Name

HY51V64164ATC

HY51V64164ALTC

HY51V64164ASLTC

HY51V65164ATC

HY51V65164ALTC

Refresh

Power

Package

8K

4K

50Pin TSOP-II

L-part

*SL-part

L-part

HY51V65164ASLTC

*SL-part

*SL : Self refresh with low power.

This document is a general product description and is subject to change without notice. Hyundai electronics does not assume any responsibility for use of

circuits described. No patent licences are implied

Hyundai Semiconductor

Rev.12/Sep.98

1

HY51V64164A,HY51V65164A

FUNCTIONAL BLOCK DIAGRAM

DQ0 ~ DQ15

8

Data Input Buffer

Data Output Buffer

OE

DQ0~7

DQ8~15

DQ0~7

DQ8~15

WE

8

LCAS

UCAS

CAS Clock

Generator

(9/10)*

Cloumn

A0

A1

Predecoder

Column Decoder

A2

Sense Amp

I/O Gate

A3

A4

A5

A6

Refresh Controller

Refresh Counter

A7

A8

A9

A10

A11

*(A12)

Row

Decoder

Memory Array

4,194,304x16

Row Predecoder

(13/12)*

RAS Clock

Generator

RAS

VCC

VSS

Substrate Bias

Generator

X32 Parallel

Test

*(A12) for 8K refresh part

(8K Refresh / 4K Refresh)*

4Mx16,EDO DRAM

Rev.12/Sep.98

2

HY51V64164A,HY51V65164A

PIN CONFIGURATION (Marking Side)

VCC

DQ0

DQ1

DQ2

DQ3

VCC

DQ4

DQ5

DQ6

DQ7

N.C

VCC

WE

RAS

N.C

A0

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

50

49

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

32

31

30

29

28

27

26

VSS

·

DQ15

DQ14

DQ13

DQ12

VSS

DQ11

DQ10

DQ9

DQ8

N.C

VSS

LCAS

UCAS

OE

N.C

A12(N.C)*

A11

A10

A1

A2

A3

A4

A9

A8

A7

A6

A5

VCC

VSS

50Pin Plastic TSOP- II (400mil)

A12(N.C)* : For 4K refresh product

PIN DESCRIPTION

Pin Name

/RAS

Parameter

Row Address Strobe

/CAS

Column Address Strobe

Write Enable

/WE

/OE

Output Enable

A0~A12

A0~A11

DQ0~DQ15

Vcc

Address Input (8K Refresh Product)

Address Input (4K Refresh Product)

Data In/Out

Power (3.3V)

Vss

Ground

NC

No Connection

4Mx16,EDO DRAM

Rev.12/Sep.98

3

HY51V64164A,HY51V65164A

ABSOLUTE MAXIMUM RATING

Symbol

Parameter

Rating

0 to 70

-55 to 150

-0.5 to 6.0

-0.5 to 4.6

50

Unit

TA

Ambient Temperature

°C

TSTG

Storage Temperature

°C

VIN, VOUT

VCC

Voltage on Any Pin relative to VSS

Voltage on VCC relative to VSS

Short Circuit Output Current

Power Dissipation

V

IOS

mA

PD

1

W

TSOLDER

Soldering Temperature Ÿ Time

260 Ÿ 10

°C Ÿ sec

Note : Operation at or above Absolute Maximum Ratings could adversely affect device reliability and cause permanent

damage.

RECOMMENDED DC OPERATING CONDITIONS

(TA = 0°C to 70°C )

Symbol

VCC

Parameter

Min

3.0

Typ

Max

3.6

UNIT

Power Supply Voltage

Input High Voltage

Input Low Voltage

3.3

V

VIH

2.0

-

VCC+0.3¹⁾

0.8

VIL

-0.3²⁾

Note : All voltages are referenced to VSS.

1) 6.0V at pulse width 10ns which is measured at VCC.

2) -1.0V at pulse width 10ns which is measured at VSS.

DC AND OPERATING CHARACTERISTICS

Symbol

Parameter

Test condition

VSS £ VIN £ VCC + 0.3

Min

Max

Unit

ILI

Input Leakage Current

(Any input)

-5

5

mA

V

All other pins not under test = VSS

ILO

Output Leakage Current

(Any input)

VSS £ VOUT £ VCC

/RAS&/CAS at VIH

-5

-

VOL

VOH

Output Low Voltage

Output High Voltage

IOL = 2.0mA

IOL = -2.0mA

0.4

-

2.4

V

4Mx16,EDO DRAM

Rev.12/Sep.98

4

HY51V64164A,HY51V65164A

DC CHARACTERISTICS

(TA = 0°C to 70°C , VCC = 3.3 ± 0.3V , VSS = 0V, unless otherwise noted.)

Max. Current

Symbol

Parameter

Test condition

Speed

Unit

8K refresh

4K refresh

ICC1

ICC2

ICC3

ICC4

ICC5

ICC6

Operating Current

/RAS, /CAS Cycling

tRC = tRC(min.)

50

60

110

90

140

120

mA

LVTTL Standby

Current

/RAS, /CAS ³ VIH

Other inputs ³ VSS

1

/RAS-only Refresh

Current

/RAS Cycling,/CAS = VIH

tRC = tRC(min.)

50

60

110

90

140

120

EDO mode Current

/CAS Cycling, /RAS = VIL

tHPC = tHPC(min.)

50

60

120

100

130

110

CMOS Standby

Current

500

300

500

300

/RAS = /CAS ³ VCC - 0.2V

L-part

/CAS-before-/RAS

Refresh Current

50

60

140

120

140

120

tRC = tRC(min.)

VIH = VCC - 0.2V, VIL = 0.2V

/CAS = CBR cycling or 0.2V

/OE&/WE = VIH = VCC - 0.2V

Address = Don’t care

DQ0~DQ15 = Open, tRAS £ 300ns

tRC=31.25uS

ICC7

Battery Back-up

Current (L-part)

550

450

550

450

mA

ICC8

Self Refresh Current

(L-part)

/RAS&/CAS = 0.2V

Other pins are same as ICC7

Note

1. ICC1, ICC3, ICC4 and ICC6 depend on output loading and cycle rates(tRC and tHPC).

2. Specified values are obtained with output unloaded.

3. ICC is specified as an average current. In ICC1, ICC3, ICC6, address can be changed only once while /RAS=VIL. In ICC4,

address can be changed maximum once while /CAS=VIH withen one EDO mode cycle time tHPC.

4Mx16,EDO DRAM

Rev.12/Sep.98

5

HY51V64164A,HY51V65164A

AC CHARACTERISTICS

(TA = 0 °C to 70 °C, VCC = 3.3 ± 0.3V , VSS = 0V, unless otherwise noted.)

50ns

Max

60ns

Max

#

Symbol

Parameter

Unit

Note

Min

84

120

20

57

-

Min

104

140

25

65

-

1

2

3

4

5

6

7

8

9

tRC

Random read or write cycle time

Read-modify-write cycle time

EDO mode cycle time

-

ns

tRWC

tHPC

tHPRWC

tRAC

tCAC

tAA

-

EDO mode read-modify-write cycle time

Access time from /RAS

-

50

60

4,5,10,11

Access time from /CAS

-

13

-

15

4,5,10

Access time from column address

Access time from /CAS precharge

/CAS to output low impedance

Output buffer turn-off delay from /CAS

/OE to output in low impedance

Transition time(rise and fall)

/RAS precharge time

-

25

-

30

4,5,11

tCPA

tCLZ

-

30

-

35

4

3

0

-

0

-

10 tCEZ

11 tOLZ

12 tT

0

10

0

15

0

-

0

-

2

50

2

50

4

13 tRP

30

50

13

40

8

-

40

60

15

45

10

20

15

5

-

14 tRAS

15 tRASP

16 tRSH

17 tCSH

18 tCAS

19 tRCD

20 tRAD

21 tCRP

22 tCP

/RAS pulse width

10K

/RAS pulse width(EDO mode)

/RAS hold time

100K

-

/CAS hold time

-

/CAS pulse width

10K

/RAS to /CAS delay time

15

13

5

37

25

-

45

30

-

10

11

/RAS to column address delay time

/CAS to /RAS precharge time

/CAS precharge time

8

-

10

0

-

15

23 tASR

24 tRAH

25 tASC

26 tCAH

27 tRAL

28 tRCS

29 tRCH

30 tRRH

31 tWCH

Row address set-up time

0

-

Row address hold time

8

-

10

0

-

Column address set-up time

Column address hold time

Column address to /RAS lead time

Read command set-up time

Read command hold time referenced to /CAS

Read command hold time referenced to /RAS

Write command hold time

0

-

14

8

-

10

30

0

-

25

0

-

0

-

0

-

7

0

-

0

-

10

-

10

-

4Mx16,EDO DRAM

Rev.12/Sep.98

6

HY51V64164A,HY51V65164A

AC CHARACTERISTICS

Continued

50ns

Max

60ns

Max

#

Symbol

Parameter

Write command pulse width

Unit

Note

Min

8

Min

10

15

10

0

32 tWP

33 tRWL

34 tCWL

35 tDS

36 tDH

-

ns

ms

ns

Write command to /RAS lead time

Write command to /CAS lead time

Data-in set-up time

15

8

-

17

8,20

12,13

9

0

-

Data-in hold time

7

-

10

-

Refresh period(4096 cycles)

Refresh period(8192 cycles)

Refresh period(L-part)

-

64

37 tREF

-

64

-

64

-

128

-

128

38 tWCS

39 tCWD

40 tRWD

41 tAWD

42 tCSR

43 tCHR

44 tRPC

45 tCPT

46 tROH

47 tOEA

48 tOED

49 tOEZ

50 tOEH

51 tCPWD

52 tRHCP

53 tWRP

54 tWRH

55 tWTS

56 tWTH

57 tRASS

58 tRPS

59 tCHS

60 tDOH

Write command set-up time

/CAS to /WE delay time

0

-

0

-

34

70

45

5

36

80

50

5

9,16

9

/RAS to /WE delay time

-

Column address to /WE delay time

/CAS set-up time(CBR cycle)

/CAS hold time(CBR cycle)

/RAS to /CAS precharge time

/CAS precharge time(CBR counter test)

/RAS hold time referenced to /OE

/OE access time

-

9

-

18

10

5

-

10

5

-

19

-

25

5

-

30

5

-

13

-

15

-

/OE to data delay

13

0

15

0

Output buffer turn-off delay time from /OE

/OE command hold time

10

-

15

-

6

13

45

30

10

100K

100

-50

5

15

54

35

10

100K

110

-50

5

/WE delay time from /CAS precharge

/RAS hold time from /CAS precharge

/WE to /RAS precharge time(CBR cycle)

/WE to /RAS hold time(CBR cycle)

Write command set-up time(test mode in)

Write command hold time(test mode in)

/RAS pulse width(self refresh)

/RAS precharge time(self refresh)

/CAS hold time(self refresh)

Output data hold time

-

4Mx16,EDO DRAM

Rev.12/Sep.98

7

HY51V64164A,HY51V65164A

AC CHARACTERISTICS

Continued

50ns

Max

60ns

Max

#

Symbol

Parameter

Unit

Note

Min

0

Min

0

61 tREZ

62 tWEZ

63 tWED

64 tOEP

65 tWPE

66 tOCH

67 tCHO

Output buffer turn-off delay from /RAS

Output buffer turn-off delay from /WE

/WE to data delay time

10

-

15

-

ns

6

0

15

5

15

5

/OE precharge time

-

/WE pulse width(EDO cycle)

/OE to /CAS hold time

5

-

5

-

5

-

5

-

/CAS hold time to /OE

5

-

5

-

4Mx16,EDO DRAM

Rev.12/Sep.98

8

HY51V64164A,HY51V65164A

TEST MODE

50ns

Max

60ns

Max

#

Symbol

Parameter

Unit

Note

Min

89

125

25

62

-

Min

109

145

30

70

-

1

2

3

4

5

6

7

8

tRC

Random read or write cycle time

Read-modify-write cycle time

EDO mode cycle time

-

ns

tRWC

tHPC

tHPRWC

tRAC

tCAC

tAA

-

EDO mode read-modify-write cycle time

Access time from /RAS

-

55

65

4,5,10,11

4,5,10

4,5,11

4

Access time from /CAS

-

18

-

20

Access time from column address

Access time from /CAS precharge

/RAS pulse width

-

30

-

35

tCPA

-

35

-

40

14 tRAS

15 tRASP

16 tRSH

17 tCSH

18 tCAS

27 tRAL

39 tCWD

40 tRWD

41 tAWD

47 tOEA

48 tOED

50 tOEH

51 tCPWD

55

20

45

13

30

39

75

50

-

10K

65

20

55

15

35

41

85

55

-

10K

/RAS pulse width(EDO mode)

/RAS hold time

100K

-

4

/CAS hold time

-

/CAS pulse width

10K

Column address to /RAS lead time

/CAS to /WE delay time

/RAS to /WE delay time

Column address to /WE delay time

/OE access time

-

16

9

-

18

-

20

-

/OE to data delay

18

50

20

59

/OE command hold time

/WE delay time from /CAS precharge

-

9

4Mx16,EDO DRAM

Rev.12/Sep.98

9

HY51V64164A,HY51V65164A

NOTE

1. An initial pause of 200ms is required after power-up followed by 8 /RAS-only refresh cycles before proper device

operation is achieved. In case of using internal refresh counter, a minimum of 8 /CAS- before-/RAS initialization

cycles instead of 8 /RAS-only refresh cycles are required. The device should be carefully initialized to be prevented

from being entered into multi bit parallel test mode during initialization.

2. If /RAS=VSS during power-up, the HY51V64164A, HY51V65164A could begin an active cycle. This condition results in

higher current than necessary current which is demanded from the power supply during power-up.

3. It is recommended that /RAS and /CAS track with Vcc during power-up or be held at a valid VIH in order to minimize

the power-up current.

4. VIH(min.) and VIL(max.) are reference levels for measuring timing of input signals. Transition times are measured

between VIH(min.) and VIL(max.), and are assumed to be 2ns for all inputs.

5. Measured at VOH=2.0V and VOL=0.8V with a load equivalent to 1TTL loads and 100pF.

6. tWEZ, tREZ, tCEZ and tOEZ define the time at which the output achieves the open circuit condition and is not referenced

to output voltage levels.

7. Either tRCH or tRRH must be satisfied for a read cycle.

8. These parameters are referenced to /CAS leading edge in early write cycles and to /WE leading edge in read-modify-

write cycles and late write cycle.

9. tWCS, tRWD, tCWD, tAWD and tCPWD are not restrictive operating parameters. They are included in the data sheet as

electrical characteristics only. If tWCS ³ tWCS(min.), the cycle is an early write cycle and data out pin will remain open

circuit (high impedance) through the entire cycle. If tRWD ³ tRWD(min.), tCWD ³ tCWD(min.), tAWD ³ tAWD(min), and tCPWD ³

tCPWD(min.), the cycle is a read-modify-write cycle and data out will contain data read from the selected cell. If neither

of the above sets of conditions is satisfied, the condition of the data out (at access time) is indeterminate.

10.Operation within the tRCD(max.) limit ensures that tRAC(max.) can be met. tRCD(max.) is specified as a reference point only.

If tRCD is greater than the specified tRCD(max.) limit, then access time is controlled by tCAC.

11.Operation within the tRAD(max.) limit ensures that tRAC(max.) can be met. tRAD(max.) is specified as a reference point only.

If tRAD is greater than the specified tRAD(max.) limit, then access time is controlled by tAA.

12.tREF(max)=128ms is applied to L-parts.

13.A burst of 4096(4K refresh part) /RAS-only refresh cycles must be executed within 64ms (128ms for L-parts) after

exiting self refresh.A burst of 8192(8K refresh part) /RAS-only refresh cycles must be executed within 64ms (128ms

for L-parts) after exiting self refresh.(CBR refresh & Hidden refresh : 4K cycle/64ms)

14.tASC,tCAH are referenced to the earlier /CAS falling edge.

15.tCP is specified from the last /CAS rising edge in the previous to the first /CAS falling edge in the next cycle.

16.tCWD is referenced to the later /CAS falling edge at word read-modifiy-write cycle.

17.tCWL is specified from /WE falling edge to the earlier /CAS rising edge.

18.tCSR is referenced to the earlier /CAS falling before /RAS transition low.

19.tCHR is referenced to the later /CAS rising high after /RAS transition low.

20.tDS is specified for the earlier /CAS falling edge and tDH is specified by the later /CAS falling edge in early write cycle.

CAPACITANCE

(TA = 0°C to 70°C , VCC = 3.3 ± 0.3V, VSS = 0V, f = 1MHz, unless otherwise noted.)

Symbol

Parameter

Input Capacitance (A0~A12)

Typ.

Max

Unit

pF

CIN1

-

5

7

CIN2

CDQ

Input Capacitance (/RAS, /CAS, /WE, /OE)

Data Input / Output Capacitance (DQ0~DQ15)

pF

4Mx16,EDO DRAM

Rev.12/Sep.98

10

型号:	HY51V65164ATC-60
是否Rohs认证：	不符合
生命周期：	Obsolete
IHS 制造商：	SK HYNIX INC
零件包装代码：	TSOP2
包装说明：	TSOP2, TSOP50,.46,32
针数：	50
Reach Compliance Code：	compliant
ECCN代码：	EAR99
HTS代码：	8542.32.00.02
风险等级：	5.28
访问模式：	FAST PAGE WITH EDO
最长访问时间：	60 ns
其他特性：	RAS ONLY/CAS BEFORE RAS/HIDDEN/SELF REFRESH
I/O 类型：	COMMON
JESD-30 代码：	R-PDSO-G50
JESD-609代码：	e0
长度：	20.95 mm
内存密度：	67108864 bit
内存集成电路类型：	EDO DRAM
内存宽度：	16
功能数量：	1
端口数量：	1
端子数量：	50
字数：	4194304 words
字数代码：	4000000
工作模式：	ASYNCHRONOUS
最高工作温度：	70 °C
最低工作温度：
组织：	4MX16
输出特性：	3-STATE
封装主体材料：	PLASTIC/EPOXY
封装代码：	TSOP2
封装等效代码：	TSOP50,.46,32
封装形状：	RECTANGULAR
封装形式：	SMALL OUTLINE, THIN PROFILE
电源：	3.3 V
认证状态：	Not Qualified
刷新周期：	4096
座面最大高度：	1.2 mm
自我刷新：	NO
最大待机电流：	0.0005 A
子类别：	DRAMs
最大压摆率：	0.12 mA
最大供电电压 (Vsup)：	3.6 V
最小供电电压 (Vsup)：	3 V
标称供电电压 (Vsup)：	3.3 V
表面贴装：	YES
技术：	CMOS
温度等级：	COMMERCIAL
端子面层：	Tin/Lead (Sn/Pb)
端子形式：	GULL WING
端子节距：	0.8 mm
端子位置：	DUAL
宽度：	10.16 mm
Base Number Matches：	1

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