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    产品型号HY57V283220LT-7的Datasheet PDF文件预览

    HY57V283220(L)T(P)/ HY5V22(L)F(P)  
    4 Banks x 1M x 32Bit Synchronous DRAM  
    Revision History  
    Revision No.  
    History  
    Remark  
    0.1  
    0.2  
    Defined Preliminary Specification  
    1) Modified FBGA Ball Configuration Typo.  
    2) Changed Functional Block Diagram from A10 to A11.  
    3) Changed VDD min from 3.0V to 3.135V.  
    4) Changed Cap. Value from C11, 3, 5 to 4pf & C12, 3.8 to 4pf.  
    5) Insert tAC2 Value.  
    6) Insdrt tRAS & CLK Value.  
    0.3  
    0.4  
    0.5  
    0.6  
    0.7  
    Defined IDD Spec.  
    Delited Preliminary.  
    Changed IDD Spec.  
    133MHz Speed Added  
    Changed FBGA Package Size from 11x13 to 8x13.  
    1) Changed VDD min from 3.135V to 3.0V.  
    2) Changed VIL min from VSSQ-0.3V to -0.3V.  
    0.8  
    0.9  
    Modified of size erra. (Page15)  
    (Equation : 13.00 ± 10 -> 13.00 ± 0.10)  
    This document is a general product description and is subject to change without notice. Hynix Semiconductor Inc. does not assume  
    any responsibility for use of circuits described. No patent licenses are implied.  
    Rev. 0.9 / July 2004  
    HY57V283220(L)T(P)/ HY5V22(L)F(P)  
    4 Banks x 1M x 32Bit Synchronous DRAM  
    DESCRIPTION  
    The Hynix HY57V283220(L)T(P) / HY5V22(L)F(P) is a 134,217,728-bit CMOS Synchronous DRAM, ideally suited for the  
    memory applications which require wide data I/O and high bandwidth. HY57V283220(L)T(P) / HY5V22(L)F(P) is orga-  
    nized as 4banks of 1,048,576x32.  
    HY57V283220(L)T(P) / HY5V22(L)F(P) is offering fully synchronous operation referenced to a positive edge of the  
    clock. All inputs and outputs are synchronized with the rising edge of the clock input. The data paths are internally  
    pipelined to achieve very high bandwidth. All input and output voltage levels are compatible with LVTTL.  
    Programmable options include the length of pipeline (Read latency of 2 or 3), the number of consecutive read or write  
    cycles initiated by a single control command (Burst length of 1,2,4,8 or full page), and the burst count  
    sequence(sequential or interleave). A burst of read or write cycles in progress can be terminated by a burst terminate  
    command or can be interrupted and replaced by a new burst read or write command on any cycle. (This pipelined  
    design is not restricted by a `2N` rule.)  
    FEATURES  
    •
    •
    •
    •
    JEDEC standard 3.3V power supply  
    •
    •
    •
    Auto refresh and self refresh  
    All device pins are compatible with LVTTL interface  
    86TSOP-II, 90Ball FBGA with 0.8mm of pin pitch  
    4096 refresh cycles / 64ms  
    Programmable Burst Length and Burst Type  
    - 1, 2, 4, 8 or full page for Sequential Burst  
    - 1, 2, 4 or 8 for Interleave Burst  
    Programmable CAS Latency ; 2, 3 Clocks  
    Burst Read Single Write operation  
    All inputs and outputs referenced to positive edge of  
    system clock  
    •
    •
    Data mask function by DQM0,1,2 and 3  
    Internal four banks operation  
    •
    •
    ORDERING INFORMATION  
    Part No.  
    Clock Frequency  
    Organization  
    Interface  
    Package  
    HY57V283220(L)T(P)-5  
    HY5V22(L)F(P)-5  
    200MHz  
    HY57V283220(L)T(P)-55  
    HY5V22(L)F(P)-55  
    183MHz  
    166MHz  
    143MHz  
    133MHz  
    125MHz  
    100MHz  
    100MHz  
    HY57V283220(L)T(P)-6  
    HY5V22(L)F(P)-6  
    HY57V283220(L)T(P)-7  
    HY5V22(L)F(P)-7  
    86TSOP-II  
    90Ball FBGA  
    4Banks x 1Mbits x32  
    LVTTL  
    HY57V283220(L)T(P)-H  
    HY5V22(L)F(P)-H  
    HY57V283220(L)T(P)-8  
    HY5V22(L)F(P)-8  
    HY57V283220(L)T(P)-P  
    HY5V22(L)F(P)-P  
    HY57V283220(L)T(P)-S  
    HY5V22(L)F(P)-S  
    Note) Hynix supports lead free part for each speed grade with same specification.  
    This document is a general product description and is subject to change without notice. Hynix Semiconductor Inc. does not assume  
    any responsibility for use of circuits described. No patent licenses are implied.  
    Rev. 0.9 / July 2004  
    HY57V283220(L)T(P) / HY5V22(L)F(P)  
    PIN CONFIGURATION ( HY57V283220(L)T(P) Series)  
    V
    D D  
    V
    S S  
    D Q 1 5  
    S S Q  
    V
    D Q 1 4  
    D Q 1 3  
    D D Q  
    V
    D Q 1 2  
    D Q 1 1  
    D Q 0  
    D D Q  
    D Q 1  
    D Q 2  
    V
    V
    S S Q  
    D Q 3  
    D Q 4  
    D D Q  
    D Q 5  
    D Q 6  
    V
    V
    S S Q  
    D Q 1 0  
    D Q 9  
    V
    S S Q  
    D D Q  
    V
    D Q 7  
    N C  
    D D  
    D Q 8  
    N C  
    V
    S S  
    V
    D Q M 0  
    /W E  
    /C A S  
    /R A S  
    /C S  
    A 1 1  
    B A 0  
    B A 1  
    A 1 0 /A P  
    A 0  
    A 1  
    A 2  
    D Q M 2  
    D Q M 1  
    N C  
    N C  
    C L K  
    C K E  
    A 9  
    A 8  
    A 7  
    A 6  
    A 5  
    A 4  
    A 3  
    D Q M 3  
    V
    D D  
    S S  
    V
    N C  
    D Q 1 6  
    S S Q  
    N C  
    D Q 3 1  
    V
    V
    D D Q  
    D Q 1 7  
    D Q 1 8  
    D D Q  
    D Q 3 0  
    D Q 2 9  
    V
    V
    S S Q  
    D Q 1 9  
    D Q 2 0  
    S S Q  
    D Q 2 8  
    D Q 2 7  
    V
    D D Q  
    V
    D Q 2 1  
    D Q 2 2  
    D D Q  
    D Q 2 3  
    D D  
    D Q 2 6  
    D Q 2 5  
    V
    S S Q  
    D Q 2 4  
    S S  
    V
    V
    V
    PIN DESCRIPTION  
    PIN  
    PIN NAME  
    DESCRIPTION  
    The system clock input. All other inputs are registered to the SDRAM  
    on the rising edge of CLK.  
    CLK  
    Clock  
    Controls internal clock signal and when deactivated, the SDRAM will be one  
    of the states among power down, suspend or self refresh  
    CKE  
    Clock Enable  
    Chip Select  
    CS  
    Enables or disables all inputs except CLK, CKE and DQM  
    Selects bank to be activated during RAS activity  
    Selects bank to be read/written during CAS activity  
    BA0, BA1  
    Bank Address  
    Row Address : RA0 ~ RA11, Column Address : CA0 ~ CA7  
    Auto-precharge flag : A10  
    A0 ~ A11  
    Address  
    Row Address Strobe,  
    Column Address Strobe,  
    Write Enable  
    RAS, CAS and WE define the operation  
    Refer function truth table for details  
    RAS, CAS, WE  
    DQM0~3  
    Data Input/Output Mask  
    Data Input/Output  
    Controls output buffers in read mode and masks input data in write mode  
    Multiplexed data input / output pin  
    DQ0 ~ DQ31  
    V
    V
    DD/VSS  
    Power Supply/Ground  
    Power supply for internal circuits and input buffers  
    Power supply for output buffers  
    DDQ/VSSQ  
    Data Output Power/Ground  
    No Connection  
    NC  
    No connection  
    Rev. 0.9 / July 2004  
    3
    HY57V283220(L)T(P) / HY5V22(L)F(P)  
    Ball CONFIGURATION ( HY5V22(L)F(P) Series)  
    1
    2
    3
    4
    5
    6
    7
    8
    9
    A
    B
    C
    D
    E
    F
    DQ26  
    DQ28  
    VSSQ  
    VSSQ  
    VDDQ  
    VSS  
    DQ24  
    VDDQ  
    DQ27  
    DQ29  
    DQ31  
    DQM3  
    A5  
    VSS  
    VSSQ  
    DQ25  
    DQ30  
    NC  
    VDD  
    VDDQ  
    DQ22  
    DQ17  
    NC  
    DQ23  
    VSSQ  
    DQ20  
    DQ18  
    DQ16  
    DQM2  
    A0  
    DQ21  
    DQ19  
    VDDQ  
    VDDQ  
    VSSQ  
    VDD  
    A3  
    A2  
    G
    H
    J
    A4  
    A6  
    A10  
    A1  
    Top View  
    A7  
    A8  
    NC  
    NC  
    BA1  
    A11  
    CLK  
    CKE  
    NC  
    A9  
    BA0  
    /CAS  
    /CS  
    /RAS  
    DQM0  
    K
    L
    DQM1  
    NC  
    /WE  
    VDDQ  
    VSSQ  
    VSSQ  
    DQ11  
    DQ13  
    DQ8  
    DQ10  
    DQ12  
    VDDQ  
    DQ15  
    VSS  
    DQ9  
    VDD  
    DQ6  
    DQ7  
    DQ5  
    VSSQ  
    VDDQ  
    VDDQ  
    DQ4  
    M
    N
    P
    R
    DQ14  
    VSSQ  
    VSS  
    DQ1  
    DQ3  
    VDDQ  
    VDD  
    VSSQ  
    DQ0  
    DQ2  
    Ball DESCRIPTION  
    PIN  
    PIN NAME  
    DESCRIPTION  
    The system clock input. All other inputs are registered to the SDRAM on the rising edge  
    of CLK.  
    CLK  
    Clock  
    Controls internal clock signal and when deactivated, the SDRAM will be one of the states  
    among power down, suspend or self refresh  
    CKE  
    Clock Enable  
    Chip Select  
    CS  
    Enables or disables all inputs except CLK, CKE and DQM  
    Selects bank to be activated during RAS activity  
    Selects bank to be read/written during CAS activity  
    BA0, BA1  
    Bank Address  
    Row Address : RA0 ~ RA11, Column Address : CA0 ~ CA7  
    Auto-precharge flag : A10  
    A0 ~ A11  
    Address  
    Row Address Strobe,  
    Column Address Strobe, Write  
    Enable  
    RAS, CAS and WE define the operation  
    Refer function truth table for details  
    RAS, CAS, WE  
    DQM0~3  
    DQ0 ~ DQ31  
    VDD/VSS  
    VDDQ/VSSQ  
    NC  
    Data Input/Output Mask  
    Data Input/Output  
    Controls output buffers in read mode and masks input data in write mode  
    Multiplexed data input / output pin  
    Power Supply/Ground  
    Data Output Power/Ground  
    No Connection  
    Power supply for internal circuits and input buffers  
    Power supply for output buffers  
    No connection  
    Rev. 0.9 / July 2004  
    4
    HY57V283220(L)T(P) / HY5V22(L)F(P)  
    FUNCTIONAL BLOCK DIAGRAM  
    1Mbit x 4banks x 32 I/O Synchronous DRAM  
    Self Refresh Logic  
    Refresh  
    Counter  
    & Timer  
    x32Bank3
    1M  
    CCLK  
    Row  
    Pre  
    1M x32 Bank 2  
    Roww AAccttiivvee  
    CCKE  
    Decoder  
    1M x32 Bank 1  
    CCS  
    1Mx32Bank0
    DDQQ00  
    RRAS  
    DDQQ11  
    Memory
    Cell
    CCAS  
    Array
    WWE  
    Colummnn  
    Activee  
    Column
    DQM00  
    Pre  
    DQM11  
    D
    e
    c
    o
    d
    e
    r
    DDQQ3300  
    DQM22  
    DDQQ3311  
    DQM33  
    Ydecoder
    Column Add
    Counter
    Bank SSeelleecctt  
    AA0  
    Address  
    A1  
    Register  
    Burst
    Counter
    AA11  
    BBA0  
    CCAASS LLaatteennccyy  
    PPiippee LLiinnee CCoonnttrrooll  
    BBA1  
    Mode Register  
    DataOutControl
    Rev. 0.9 / July 2004  
    5
    HY57V283220(L)T(P) / HY5V22(L)F(P)  
    ABSOLUTE MAXIMUM RATINGS  
    Parameter  
    Symbol  
    Rating  
    Unit  
    Ambient Temperature  
    TA  
    0 ~ 70  
    -55 ~ 125  
    -1.0 ~ 4.6  
    -1.0 ~ 4.6  
    50  
    °C  
    Storage Temperature  
    TSTG  
    °C  
    Voltage on Any Pin relative to VSS  
    Voltage on VDD relative to VSS  
    Short Circuit Output Current  
    Power Dissipation  
    VIN, VOUT  
    VDD, VDDQ  
    IOS  
    V
    V
    mA  
    PD  
    1
    W
    Soldering Temperature Þ Time  
    TSOLDER  
    260 ⋅ 10  
    °C ⋅ Sec  
    Note : Operation at above absolute maximum rating can adversely affect device reliability  
    DC OPERATING CONDITION (TA=0 to 70°C)  
    Parameter  
    Symbol  
    VDD, VDDQ  
    Min  
    Typ.  
    Max  
    Unit  
    Note  
    Power Supply Voltage  
    Input high voltage  
    Input low voltage  
    3.0  
    2.0  
    3.3  
    3.0  
    0
    3.6  
    VDDQ + 0.3  
    0.8  
    V
    V
    V
    1
    VIH  
    VIL  
    1,2  
    1,3  
    - 0.3  
    Note :  
    1.All voltages are referenced to VSS = 0V  
    2.VIH (max) is acceptable 5.6V AC pulse width with ≤3ns of duration with no input clamp diodes  
    3.VIL (min) is acceptable -2.0V AC pulse width with ≤3ns of duration with no input clamp diodes  
    AC OPERATING CONDITION (TA=0 to 70°C, 3.0V ≤VDD ≤3.6V, VSS=0V - Note1)  
    Parameter  
    AC input high / low level voltage  
    Symbol  
    Value  
    Unit  
    Note  
    VIH / VIL  
    Vtrip  
    2.4/0.4  
    1.4  
    1
    V
    V
    Input timing measurement reference level voltage  
    Input rise / fall time  
    tR / tF  
    Voutref  
    CL  
    ns  
    V
    Output timing measurement reference level  
    Output load capacitance for access time measurement  
    1.4  
    30  
    pF  
    1
    Note :  
    1.Output load to measure access times is equivalent to two TTL gates and one capacitor (30pF)  
    For details, refer to AC/DC output load circuit  
    Rev. 0.9 / July 2004  
    6
    HY57V283220(L)T(P) / HY5V22(L)F(P)  
    CAPACITANCE ( HY57V283220T Series) (TA=25°C, f=1MHz, VDD=3.3V)  
    Parameter  
    Input capacitance  
    Pin  
    Symbol  
    Min  
    Max  
    Unit  
    CLK  
    CI1  
    CI2  
    2.5  
    2.5  
    4.0  
    4.0  
    pF  
    pF  
    A0 ~ A11, BA0, BA1, CKE, CS, RAS, CAS, WE,  
    DQM0~3  
    Data input / output capacitance  
    DQ0 ~ DQ31  
    CI/O  
    4.0  
    6.5  
    pF  
    OUTPUT LOAD CIRCUIT  
    Vtt=1.4V  
    Vtt=1.4V  
    RT=500 Ω  
    RT=50 Ω  
    Output  
    Z0 = 50Ω  
    Output  
    30pF  
    30pF  
    DC Output Load Circuit  
    AC Output Load Circuit  
    DC CHARACTERISTICS I (DC operating conditions unless otherwise noted)  
    Parameter  
    Symbol  
    Min.  
    Max  
    Unit  
    Note  
    Input leakage current  
    Output leakage current  
    Output high voltage  
    Output low voltage  
    ILI  
    ILO  
    -1  
    -1  
    2.4  
    -
    1
    1
    uA  
    uA  
    V
    1
    2
    VOH  
    VOL  
    -
    IOH = -2mA  
    IOL = +2mA  
    0.4  
    V
    Note :  
    1.VIN = 0 to 3.6V, All other pins are not under test = 0V  
    2.DOUT is disabled, VOUT=0 to 3.6V  
    Rev. 0.9 / July 2004  
    7
    HY57V283220(L)T(P) / HY5V22(L)F(P)  
    DC CHARACTERISTICS II (DC operating conditions unless otherwise noted)  
    Speed  
    Parameter  
    Symbol  
    Test Condition  
    Unit  
    mA  
    Note  
    -5  
    -55  
    -6  
    -7  
    -H  
    -8  
    -P  
    S
    Burst length=1, One bank active  
    tRC ≥ tRC(min), IOL=0mA  
    Operating Current  
    IDD1  
    120  
    120  
    110  
    100  
    100  
    100  
    90  
    90  
    1
    IDD2P  
    CKE ≤ VIL(max), tCK = 10ns  
    CKE ≤ VIL(max), tCK = ∞  
    2
    1
    Precharge Standby Current  
    in power down mode  
    mA  
    IDD2PS  
    CKE ≥ VIH(min), CS ≥ VIH(min),  
    tCK = 10ns Input signals are changed one  
    time during 2clks. All other pins ≥ VDD-  
    0.2V or ≤ 0.2V  
    IDD2N  
    14  
    9
    Precharge Standby Current  
    in non power down mode  
    mA  
    mA  
    CKE ≥ VIH(min), tCK = ∞  
    Input signals are stable.  
    IDD2NS  
    IDD3P  
    7
    6
    CKE ≤ VIL(max), tCK = 10ns  
    CKE ≤ VIL(max), tCK = ∞  
    Active Standby Current  
    in power down mode  
    IDD3PS  
    CKE ≥ VIH(min), CS ≥ VIH(min),  
    tCK = 10ns Input signals are changed  
    one time during 2clks. All other pins  
    ≥ VDD-0.2V or ≤ 0.2V  
    IDD3N  
    17  
    13  
    Active Standby Current  
    in non power down mode  
    mA  
    CKE ≥ VIH(min), tCK = ∞  
    Input signals are stable.  
    IDD3NS  
    CL=3  
    230  
    -
    220  
    -
    200  
    -
    180  
    -
    180  
    -
    150  
    -
    130  
    130  
    140  
    130  
    130  
    140  
    ttCK ≥ tCK(min),  
    IOL=0mA  
    All banks active  
    Burst Mode Operating  
    Current  
    IDD4  
    IDD5  
    IDD6  
    mA  
    mA  
    mA  
    1
    CL=2  
    Auto Refresh Current  
    Self Refresh Current  
    170  
    160  
    150  
    140  
    140  
    140  
    2
    3
    4
    tRC ≥ tRC(min), All banks active  
    CKE ≤ 0.2V  
    2
    0.8  
    Note :  
    1.IDD1 and IDD4 depend on output loading and cycle rates. Specified values are measured with the output open  
    2.Min. of tRRC (Refresh RAS cycle time) is shown at AC CHARACTERISTICS II  
    3.HY57V283220T(P)(HY5V22F(P))-5/55/6/7/H/8/P/S  
    4.HY57V283220LT(P)(HY5V22LF(P))-5/55/6/7/H/8/P/S  
    Rev. 0.9 / July 2004  
    8
    HY57V283220(L)T(P) / HY5V22(L)F(P)  
    AC CHARACTERISTICS I (AC operating conditions unless otherwise noted)  
    -5  
    -55  
    -6  
    -7  
    -H  
    -8  
    -P  
    -S  
    Parameter  
    Symbol  
    Unit Note  
    Min Max Min Max Min Max Min Max Min Max Min Max Min Max Min Max  
    CAS Latency = 3  
    tCK3  
    tCK2  
    tCHW  
    tCLW  
    tAC3  
    tAC2  
    tOH  
    5
    10  
    2
    5.5  
    10  
    2.25  
    2.25  
    -
    6
    10  
    2.5  
    2.5  
    -
    7
    7.5  
    8
    -10  
    3
    3
    -
    10  
    10  
    3
    3
    -
    10  
    12  
    3
    3
    -
    ns  
    ns  
    System clock  
    cycle time  
    1000  
    1000  
    1000  
    1000  
    1000  
    1000  
    1000  
    1000  
    CAS Latency = 2  
    10  
    10  
    Clock high pulse width  
    Clock low pulse width  
    -
    -
    -
    -
    -
    -
    3
    -
    -
    3
    -
    -
    -
    -
    -
    -
    -
    -
    ns  
    ns  
    ns  
    ns  
    ns  
    ns  
    ns  
    ns  
    ns  
    ns  
    ns  
    ns  
    ns  
    ns  
    ns  
    ns  
    1
    1
    2
    3
    3
    CAS Latency = 3  
    -
    4.5  
    6
    -
    5
    6
    -
    5.5  
    6
    -
    -
    5.5  
    6
    -
    -
    5.5  
    6
    -
    6
    6
    -
    6
    6
    -
    6
    6
    -
    Access time from  
    clock  
    2
    CAS Latency = 2  
    -
    -
    -
    -
    -
    -
    -
    -
    Data-out hold time  
    1.5  
    1.5  
    1
    2
    2
    2
    1.75  
    1
    2
    1.75  
    1
    2
    2
    1
    2
    1
    2
    1
    2
    1
    1
    -
    2
    2
    1
    2
    1
    2
    1
    2
    1
    1
    -
    2
    2
    1
    2
    1
    2
    1
    2
    1
    1
    -
    3
    1
    1
    1
    1
    1
    1
    1
    1
    Data-Input setup time  
    Data-Input hold time  
    Address setup time  
    Address hold time  
    tDS  
    -
    1.5  
    1
    -
    1.5  
    1
    -
    -
    -
    -
    -
    -
    tDH  
    -
    -
    -
    -
    -
    -
    -
    -
    tAS  
    1.5  
    1
    -
    1.5  
    1
    -
    1.5  
    1
    -
    1.75  
    1
    -
    1.75  
    1
    -
    -
    -
    -
    tAH  
    -
    -
    -
    -
    -
    -
    -
    -
    CKE setup time  
    tCKS  
    tCKH  
    tCS  
    1.5  
    1
    -
    1.5  
    1
    -
    1.5  
    1
    -
    1.75  
    1
    -
    1.75  
    1
    -
    -
    -
    -
    CKE hold time  
    -
    -
    -
    -
    -
    -
    -
    -
    Command setup time  
    Command hold time  
    CLK to data output in low Z-time  
    1.5  
    1
    -
    1.5  
    1
    -
    1.5  
    1
    -
    1.75  
    1
    -
    1.75  
    1
    -
    -
    -
    -
    tCH  
    -
    -
    -
    -
    -
    -
    -
    -
    tOLZ  
    tOHZ3  
    tOHZ2  
    1
    -
    1
    -
    1
    -
    1
    -
    1
    -
    -
    -
    -
    CAS Latency = 3  
    -
    4.5  
    6
    -
    5
    6
    -
    5.5  
    6
    -
    5.5  
    6
    -
    5.5  
    6
    6
    6
    6
    6
    6
    6
    CLK to data output  
    in high Z-time  
    CAS Latency = 2  
    -
    -
    -
    -
    -
    -
    -
    -
    Note :  
    1.Assume tR / tF (input rise and fall time ) is 1ns  
    2.Access times to be measured with input signals of 1v/ns edge rate, 0.8v to 2.0v  
    3.Data-out hold time to be measured under 30pF load condition, without Vt termination  
    Rev. 0.9 / July 2004  
    9
    HY57V283220(L)T(P) / HY5V22(L)F(P)  
    AC CHARACTERISTICS II (AC operating conditions unless otherwise noted)  
    -5  
    -55  
    -6  
    -7  
    -H  
    -8  
    -P  
    -S  
    Parameter  
    Symbol  
    Unit Note  
    Min Max Min Max Min Max Min Max Min Max Min Max Min Max Min Max  
    Operation  
    tRC  
    55  
    55  
    15  
    -
    -
    -
    55  
    55  
    -
    -
    -
    60  
    60  
    18  
    -
    -
    -
    63  
    63  
    20  
    -
    -
    -
    63  
    63  
    20  
    -
    -
    -
    64  
    64  
    20  
    -
    -
    -
    70  
    70  
    20  
    -
    -
    -
    70  
    70  
    20  
    -
    -
    -
    ns  
    ns  
    ns  
    RAS cycle time  
    Auto Refresh  
    tRRC  
    tRCD  
    RAS to CAS delay  
    RAS active time  
    16.5  
    100  
    K
    100  
    K
    100  
    K
    100  
    K
    100  
    K
    100  
    K
    100  
    K
    100  
    K
    tRAS  
    38.7  
    38.7  
    42  
    42  
    42  
    48  
    50  
    50  
    ns  
    RAS precharge time  
    tRP  
    15  
    2
    1
    0
    1
    4
    2
    0
    2
    3
    2
    1
    1
    -
    -
    -
    16.5  
    2
    -
    -
    18  
    2
    1
    0
    1
    4
    2
    0
    2
    3
    2
    1
    1
    -
    -
    -
    20  
    2
    1
    0
    1
    4
    2
    0
    2
    3
    2
    1
    1
    -
    -
    -
    20  
    2
    1
    0
    1
    4
    2
    0
    2
    3
    2
    1
    1
    -
    -
    -
    20  
    2
    1
    0
    1
    4
    2
    0
    2
    3
    2
    1
    1
    -
    -
    -
    20  
    20  
    1
    -
    -
    20  
    20  
    1
    -
    -
    ns  
    RAS to RAS bank active delay  
    CAS to CAS delay  
    tRRD  
    tCCD  
    tWTL  
    tDPL  
    tDAL  
    tDQZ  
    tDQM  
    tMRD  
    CLK  
    CLK  
    CLK  
    CLK  
    CLK  
    CLK  
    CLK  
    CLK  
    CLK  
    CLK  
    CLK  
    -
    1
    -
    -
    -
    -
    -
    -
    -
    Write command to data-in delay  
    Data-in to precharge command  
    Data-in to active command  
    DQM to data-out Hi-Z  
    -
    0
    -
    -
    -
    -
    -
    0
    -
    0
    -
    -
    1
    -
    -
    -
    -
    -
    1
    -
    1
    -
    -
    4
    -
    -
    -
    -
    -
    4
    -
    4
    -
    -
    2
    -
    -
    -
    -
    -
    2
    -
    2
    -
    DQM to data-in mask  
    -
    0
    -
    -
    -
    -
    -
    0
    -
    0
    -
    MRS to new command  
    -
    2
    -
    -
    -
    -
    -
    2
    -
    2
    -
    CAS Latency = 3 tPROZ3  
    CAS Latency = 2 tPROZ2  
    -
    3
    -
    -
    -
    -
    -
    3
    -
    3
    -
    Precharge to data  
    output Hi-Z  
    -
    2
    -
    -
    -
    -
    -
    2
    -
    2
    -
    Power down exit time  
    Self refresh exit time  
    Refresh Time  
    tPDE  
    tSRE  
    tREF  
    -
    1
    -
    -
    -
    -
    -
    1
    -
    1
    -
    -
    1
    -
    -
    -
    -
    -
    1
    -
    1
    -
    CLK  
    ms  
    1
    64  
    -
    64  
    64  
    64  
    64  
    64  
    -
    64  
    -
    64  
    Note :  
    1. A new command can be given tRRC after self refresh exit  
    Rev. 0.9 / July 2004  
    10  
    HY57V283220(L)T(P) / HY5V22(L)F(P)  
    DEVICE OPERATING OPTION TABLE  
    HY5xxxxxxxxx(P)-5  
    CAS Latency  
    tRCD  
    tRAS  
    tRC  
    tRP  
    tAC  
    tOH  
    200MHz(5ns)  
    183MHz(5.5ns)  
    166MHz(6ns)  
    3CLKs  
    3CLKs  
    3CLKs  
    3CLKs  
    3CLKs  
    3CLKs  
    8CLKs  
    8CLKs  
    7CLKs  
    11CLKs  
    10CLKs  
    10CLKs  
    3CLKs  
    3CLKs  
    3CLKs  
    4.5ns  
    5ns  
    1.5ns  
    2ns  
    5.5ns  
    2ns  
    HY5xxxxxxxxx(P)-55  
    CAS Latency  
    tRCD  
    tRAS  
    tRC  
    tRP  
    tAC  
    tOH  
    183MHz(5.5ns)  
    166MHz(6ns)  
    143MHz(7ns)  
    3CLKs  
    3CLKs  
    3CLKs  
    3CLKs  
    3CLKs  
    3CLKs  
    7CLKs  
    7CLKs  
    6CLKs  
    10CLKs  
    10CLKs  
    9CLKs  
    3CLKs  
    3CLKs  
    3CLKs  
    5ns  
    2ns  
    2ns  
    2ns  
    5.5ns  
    5.5ns  
    HY5xxxxxxxxx(P)-6  
    CAS Latency  
    tRCD  
    tRAS  
    tRC  
    tRP  
    tAC  
    tOH  
    166MHz(6ns)  
    143MHz(7ns)  
    125MHz(8ns)  
    3CLKs  
    3CLKs  
    3CLKs  
    3CLKs  
    3CLKs  
    3CLKs  
    7CLKs  
    6CLKs  
    6CLKs  
    10CLKs  
    9CLKs  
    9CLKs  
    3CLKs  
    3CLKs  
    3CLKs  
    5.5ns  
    5.5ns  
    6ns  
    2ns  
    2ns  
    2.5ns  
    HY5xxxxxxxxx(P)-7  
    CAS Latency  
    tRCD  
    tRAS  
    tRC  
    tRP  
    tAC  
    tOH  
    143MHz(7ns)  
    125MHz(8ns)  
    100MHz(10ns)  
    3CLKs  
    3CLKs  
    2CLKs  
    3CLKs  
    3CLKs  
    2CLKs  
    6CLKs  
    6CLKs  
    5CLKs  
    9CLKs  
    9CLKs  
    7CLKs  
    3CLKs  
    3CLKs  
    2CLKs  
    5.5ns  
    6ns  
    2ns  
    2ns  
    2ns  
    6ns  
    HY5xxxxxxxxx(P)-H  
    CAS Latency  
    tRCD  
    tRAS  
    tRC  
    tRP  
    tAC  
    tOH  
    133MHz(7.5ns)  
    125MHz(8ns)  
    100MHz(10ns)  
    3CLKs  
    3CLKs  
    2CLKs  
    3CLKs  
    3CLKs  
    2CLKs  
    6CLKs  
    6CLKs  
    5CLKs  
    9CLKs  
    9CLKs  
    7CLKs  
    3CLKs  
    3CLKs  
    2CLKs  
    5.5ns  
    6ns  
    2ns  
    2ns  
    2ns  
    6ns  
    HY5xxxxxxxxx(P)-8  
    CAS Latency  
    tRCD  
    tRAS  
    tRC  
    tRP  
    tAC  
    tOH  
    125MHz(8ns)  
    100MHz(10ns)  
    83MHz(12ns)  
    3CLKs  
    2CLKs  
    2CLKs  
    3CLKs  
    2CLKs  
    2CLKs  
    6CLKs  
    5CLKs  
    4CLKs  
    9CLKs  
    7CLKs  
    6CLKs  
    3CLKs  
    2CLKs  
    2CLKs  
    6ns  
    6ns  
    6ns  
    2ns  
    2ns  
    2.5ns  
    Rev. 0.9 / July 2004  
    11  
    HY57V283220(L)T(P) / HY5V22(L)F(P)  
    HY5xxxxxxxxx(P)-P  
    CAS Latency  
    tRCD  
    tRAS  
    tRC  
    tRP  
    tAC  
    tOH  
    100MHz(10ns)  
    83MHz(12ns)  
    66MHz(15ns)  
    2CLKs  
    2CLKs  
    2CLKs  
    2CLKs  
    2CLKs  
    2CLKs  
    5CLKs  
    5CLKs  
    4CLKs  
    7CLKs  
    7CLKs  
    6CLKs  
    2CLKs  
    2CLKs  
    2CLKs  
    6ns  
    6ns  
    6ns  
    2ns  
    2.5ns  
    2.5ns  
    HY5xxxxxxxxx(P)-S  
    CAS Latency  
    tRCD  
    tRAS  
    tRC  
    tRP  
    tAC  
    tOH  
    100MHz(10ns)  
    83MHz(12ns)  
    66MHz(15ns)  
    3CLKs  
    2CLKs  
    2CLKs  
    2CLKs  
    2CLKs  
    2CLKs  
    5CLKs  
    5CLKs  
    4CLKs  
    7CLKs  
    7CLKs  
    6CLKs  
    2CLKs  
    2CLKs  
    2CLKs  
    6ns  
    6ns  
    6ns  
    2ns  
    2.5ns  
    2.5ns  
    Rev. 0.9 / July 2004  
    12  
    HY57V283220(L)T(P) / HY5V22(L)F(P)  
    COMMAND TRUTH TABLE  
    A10/  
    AP  
    ADDR  
    Command  
    CKEn-1  
    CKEn  
    CS  
    RAS  
    CAS  
    WE  
    DQM  
    BA  
    Note  
    Mode Register Set  
    H
    H
    H
    H
    X
    L
    H
    L
    L
    X
    H
    L
    L
    X
    H
    H
    L
    X
    H
    H
    X
    OP code  
    No Operation  
    X
    X
    X
    X
    X
    X
    X
    Bank Active  
    L
    RA  
    V
    V
    Read  
    L
    H
    L
    L
    L
    H
    H
    L
    L
    L
    H
    L
    CA  
    CA  
    X
    Read with Autoprecharge  
    Write  
    H
    H
    X
    X
    X
    V
    Write with Autoprecharge  
    Precharge All Banks  
    Precharge selected Bank  
    Burst Stop  
    H
    H
    L
    X
    V
    X
    X
    L
    L
    H
    H
    L
    L
    H
    H
    H
    H
    X
    L
    X
    V
    X
    X
    X
    X
    DQM  
    Auto Refresh  
    H
    X
    L
    L
    L
    L
    L
    H
    L
    A9 Pin High  
    (Other Pins OP code)  
    Burst-Read-Single-WRITE  
    H
    H
    L
    X
    X
    3
    Entry  
    L
    H
    L
    L
    X
    H
    X
    H
    X
    H
    X
    V
    L
    X
    H
    X
    H
    X
    H
    X
    V
    H
    X
    H
    X
    H
    X
    H
    X
    V
    Self Refresh1  
    X
    Exit  
    Entry  
    Exit  
    L
    H
    L
    H
    L
    X
    X
    X
    H
    L
    Precharge power  
    down  
    X
    X
    H
    L
    H
    H
    L
    Entry  
    Exit  
    H
    L
    L
    X
    X
    Clock  
    Suspend  
    H
    X
    Note :  
    1. Exiting Self Refresh occurs by asynchronously bringing CKE from low to high  
    2. X = Don¢t care, H = Logic High, L = Logic Low. BA =Bank Address, RA = Row Address, CA = Column Address,  
    Opcode = Operand Code, NOP = No Operation  
    3. The burst read sigle write mode is entered by programming the write burst mode bit (A9) in the mode register to a logic 1.  
    Rev. 0.9 / July 2004  
    13  
    HY57V283220(L)T(P) / HY5V22(L)F(P)  
    PACKAGE INFORMATION (HY57V283220T(P) Series)  
    400mil 86pin Thin Small Outline Package  
    Unit : mm(inch)  
    11.938(0.4700)  
    11.735(0.4620)  
    22.327(0.8790)  
    22.149(0.8720)  
    10.262(0.4040)  
    10.058(0.3960)  
    0.150(0.0059)  
    0.050(0.0020)  
    1.194(0.0470)  
    0.991(0.0390)  
    5deg  
    0deg  
    0.210(0.0083)  
    0.120(0.0047)  
    0.597(0.0235)  
    0.406(0.0160)  
    0.21(0.008)  
    0.18(0.007)  
    0.50(0.0197)  
    Rev. 0.9 / July 2004  
    14  
    HY57V283220(L)T(P) / HY5V22(L)F(P)  
    PACKAGE INFORMATION (HY5V22F(P) Series)  
    90Ball FBGA with 0.8mm of pin pitch  
    (Ball-side view)  
    6.40  
    0.80(typ)  
    pin#1  
    ID  
    0.80 typ  
    13.00 ± 0.10  
    11.20  
    5.60 ± 0.5  
    6.50 ± 0.5  
    3.20 ± 0.5  
    4.00 ± 0.5  
    Ball Size  
    0.45 ± 0.05mm  
    8.00  
    0.850+/-0.075  
    1.20max  
    seating plane  
    Rev. 0.9 / July 2004  
    15  
    配单直通车
    HY57V283220LT-7产品参数
    型号:HY57V283220LT-7
    生命周期：Obsolete
    零件包装代码：TSOP2
    包装说明：TSSOP, TSSOP86,.46,20
    针数：86
    Reach Compliance Code：unknown
    ECCN代码：EAR99
    HTS代码：8542.32.00.02
    风险等级：5.83
    访问模式：FOUR BANK PAGE BURST
    最长访问时间：5.5 ns
    其他特性：AUTO/SELF REFRESH
    最大时钟频率 (fCLK)：143 MHz
    I/O 类型：COMMON
    交错的突发长度：1,2,4,8
    JESD-30 代码：R-PDSO-G86
    长度：22.238 mm
    内存密度：134217728 bit
    内存集成电路类型：SYNCHRONOUS DRAM
    内存宽度：32
    功能数量：1
    端口数量：1
    端子数量：86
    字数：4194304 words
    字数代码：4000000
    工作模式：SYNCHRONOUS
    最高工作温度：70 °C
    最低工作温度：
    组织：4MX32
    输出特性：3-STATE
    封装主体材料：PLASTIC/EPOXY
    封装代码：TSSOP
    封装等效代码：TSSOP86,.46,20
    封装形状：RECTANGULAR
    封装形式：SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
    电源：3.3 V
    认证状态：Not Qualified
    刷新周期：4096
    座面最大高度：1.194 mm
    自我刷新：YES
    连续突发长度：1,2,4,8,FP
    最大待机电流：0.001 A
    子类别：DRAMs
    最大压摆率：0.18 mA
    最大供电电压 (Vsup)：3.6 V
    最小供电电压 (Vsup)：3 V
    标称供电电压 (Vsup)：3.3 V
    表面贴装：YES
    技术：CMOS
    温度等级：COMMERCIAL
    端子形式：GULL WING
    端子节距：0.5 mm
    端子位置：DUAL
    宽度：10.16 mm
    Base Number Matches：1
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