YSS950
(b) On-chip memory access
Access to on-chip memory is performed in 32-bit units via the serial peripheral interface. Also, on-chip
memory access can be performed with register access. The following describes the two operation modes that
are provided for this LSI.
1) Burst transfer mode
Burst transfer mode can be used to download instruction code/coefficient data firmware. By using this mode,
a large amount of data can be downloaded at high speeds when initialization is executed or when the sampling
frequency is changed. The features of the burst transfer mode are as follows.
• Stops signal processing during high-speed transfers
• Muting is automatically effected during transfer period.
• Transfers from microcontrollers can be accepted immediately, without handshaking
• Both instruction code firmware and coefficient data firmware can be downloaded.
The burst transfer steps for on-chip memory access are illustrated below.
(1)
(2)
(3)
(4)
/CS
Don't care
Don't care
SCK
A
A
A
A
A
A
A
A
A+1 A+1 A+1 A+1
A+n A+n A+n A+n
D28 D29 D30 D31
D4 D5 D6 D7
SI
D0 D1 D2 D3
D28 D29 D30 D31 D0 D1 D2 D3
High-Z
SO
(OMA)
(OMAA)
A + n + 1
A
A + 1
A + n
<1> Setup:
• Initialize the checksum as necessary. （OMASUM[7:0]=0）
• Set the on-chip memory access start address (example: OMAA[20:0] = A).
• Change the serial peripheral interface pin function from register access to on-chip memory access (OMA
= 1).
<2> Start:
• Data is transferred LSB first, in 32-bit units.
• Data is captured at the rising edge of SCK in the 32nd data bit (D31).
<3> Continuation:
• Next, transfer data at consecutive address in 32-bit units.
• The on-chip memory address (OMAA[20:0]) is automatically incremented each time 32 bits of data are
written.
<4> Completion and post-completion processing:
• On-chip memory access ends (OMA = 0) automatically when /CS = H is set.
• OMAA[20:0] is notified of the start address and transfer data number. (E.G. OMAA[20:0]= A+n+1)
• OMASUM[7:0] is notified of the checksum of the transferred data.
[Note]
• Burst transfer can be interrupted by setting /CS to high level.
If burst transfer is interrupted before the rising edge of SCK in the 32nd data bit, the write operation is
not performed.
• When transferring to non-consecutive addresses or when re-executing after a transfer has been
interrupted, start from step (1) above.
• When data is at consecutive addresses, the data at the transfer start address should be transferred with
the start bit incremented each time according to the address order.
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